Principal Engineer - Digital ASIC Design (SystemVerilog)

Location: CA - San Jose - Fortune Dr (Micrel R&D), United States

Annual base salary: $70,304–$163,000

Company

hirify.global is a global technology company developing semiconductor products and solutions, with a 17,000-member workforce and a focus on employee development, innovation, and long-term stability.

What you will do

• Follow micro-architecture specifications and implement SystemVerilog RTL for complex digital IP blocks from concept through delivery.
• Drive power, performance, and area trade-offs and optimize designs to meet product targets.
• Collaborate with SoC integration teams on connectivity, top-level timing, and congestion issues.
• Lead lint, CDC, RDC, and formal verification activities.
• Work with Physical Design teams to close timing and resolve routing bottlenecks.
• Support module and system verification, post-silicon validation, bring-up, and design documentation.

Requirements

• 10+ years of experience in ASIC or FPGA digital design.
• BS or MS degree in Electrical Engineering.
• Proficiency in SystemVerilog and synchronous/asynchronous design techniques.
• Experience with the Cadence/Synopsys front-end EDA flow, including VCS, SpyGlass, Design Compiler, and PrimeTime.
• Experience with scripting, PHY or SerDes protocols, and post-silicon validation or bring-up.
• Ability to use laboratory equipment such as oscilloscopes and logic analyzers.

Nice to have

• Knowledge of IEEE 802.3.

Culture & Benefits

• Regular business hours with approximately 70% sitting, 15% standing, and 15% walking.
• Travel requirement of 0%–25%.
• Health benefits beginning on the first day of employment.
• Retirement savings plans, restricted stock units, quarterly bonus payments, and an ESPP with a two-year lookback feature.
• Employee development programs and a workplace focused on trust, respect, diversity, communication, and innovation.