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2 дня назад

Principal Digital Design Engineer

160 400 - 237 320$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Principal Digital Design Engineer (ASIC/SoC): Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated circuits with an accent on high-speed multiple clock domain designs and protocols like PCIe, CXL. Focus on full design cycle including specifications, RTL coding, verification, silicon bring-up, and improving design methodologies.

Location: San Diego, CA, USA (onsite). US export control eligibility required (US citizens, permanent residents, or protected individuals).

Salary: $160,400 - $237,320 per annum

Company

hirify.global’s semiconductor solutions power data infrastructure for enterprise, cloud, AI, and carrier architectures.

What you will do

  • Design, develop, implement, verify, and document micro-architecture and RTL for complex power management ICs.
  • Collaborate with system and chip architects for high-quality implementations.
  • Participate end-to-end in design cycle: micro-architecture docs, RTL coding, timing specs, verification test plans, silicon lab testing, and IP maintenance.
  • Produce block uArchitecture and register specs; schedule cross-functional reviews.
  • Evaluate and improve design and verification methodologies.
  • Supervise or mentor other digital design engineers; provide technical leadership.

Requirements

  • Bachelor’s in Computer Science, Electrical Engineering or related + 10-15+ years experience (Master’s/PhD + 5-10+ years).
  • Fluent in SystemVerilog RTL coding; experience in high-speed, multiple clock domain designs.
  • Expertise in PCIe, CXL protocols; familiar with SoC architectures, AXI, DDR, Ethernet.
  • RTL design, synthesis, static-timing closure, formal verification, gate-level sims, block verification.
  • Experience in micro-architecture of custom ASIC products with Chip I/O, shared memory, embedded processors.
  • Hands-on chip-development process, front-end tools; SVA assertions, formal verification tools.
  • Strong communication, documentation, cross-site collaboration; scripting (Python, Perl, Tcl, UNIX shell desirable).

Culture & Benefits

  • Comprehensive benefits: financial well-being (employee stock purchase plan), family support, mental/physical health resources, recognition awards.
  • Opportunity to shape design strategy, build and lead a world-class team in new San Diego design center.
  • Focus on purposeful innovation in AI, XPU, custom SoC for strategic customer programs.

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