Sr Principal Digital Design Engineer

TL;DR

Sr Principal Digital Design Engineer (AI SoC): Design, develop, implement, verify, and document micro-architecture and RTL for complex power management ICs and custom SoCs with an accent on high-speed multiple clock domain designs, PCIe/CXL protocols, and modern SoC architectures. Focus on full end-to-end design cycle including specs, RTL coding, verification, timing closure, silicon bring-up, and mentoring teams.

Location: Onsite in San Diego, CA, USA. This position may require access to export-controlled technology; applicants must be eligible under US export laws.

Salary: $184,400 - $272,950 per annum

Company

hirify.global builds semiconductor solutions for data infrastructure in enterprise, cloud, AI, and carrier architectures.

What you will do

• Design, develop, implement, verify, and document micro-architecture and RTL for complex power management ICs.
• Collaborate with system and chip architects on industrial-quality implementations.
• Participate in full design cycle: micro-architecture docs, RTL coding, timing specs, verification test plans, silicon lab testing, and IP maintenance.
• Produce block uArchitecture and register specs; schedule cross-functional reviews.
• Evaluate and improve design and verification methodologies.
• Supervise or mentor digital design engineers while building the San Diego design team.

Requirements

• Bachelor’s in CS/EE or related + 15+ years experience (Master’s +10-12 years, PhD +8-10 years).
• Fluent in SystemVerilog RTL coding; experience in high-speed, multiple clock domain designs.
• Expertise in PCIe, CXL protocols; familiar with SoC architectures, AXI, DDR, Ethernet.
• RTL design, synthesis, static-timing closure, formal verification, gate-level sims, block verification.
• Experience in micro-architecture of custom ASIC products with Chip I/O, shared memory, embedded processors.
• Hands-on chip development, front-end tools; SVA assertions, formal tools; scripting (Python/Perl/Tcl/UNIX desirable).
• US export control eligibility required (US citizens, permanent residents, or protected individuals).

Nice to have

• High-speed (>1 GHz) embedded processor SoCs.
• Implementation/timing closure for high-speed designs.

Culture & Benefits

• Comprehensive benefits: financial well-being (employee stock purchase), family support, mental/physical health resources, recognition awards.
• Opportunity to shape design strategy, culture, and team in new San Diego design center.
• Focus on purposeful innovation in AI and compute platforms.

Hiring process

• Interviews evaluate experience, thought process, communication; no AI tools allowed.
• Contact HR for accommodations.