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7 часов назад

PMTS ASIC Digital Design IP Engineering

167 000 - 275 000$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
PMTS ASIC Digital Design IP Engineering (Processor Microarchitecture/RTL): Leading architecture implementation, microarchitecture development, and RTL design for high-performance processor cores and SoC subsystem components with an accent on Verilog/SystemVerilog, PPA optimization, and silicon bring-up. Focus on designing pipelines, cache and memory hierarchies, MMUs, interconnects, and system controllers while solving complex latency, throughput, scalability, and performance challenges.

Location: Santa Clara, United States

Salary: $167,000–$275,000 per year

Company

hirify.global is a full-service semiconductor foundry providing design, development, and fabrication services with a global manufacturing footprint.

What you will do

  • Lead architecture implementation, microarchitecture development, and RTL design for high-performance processor cores and SoC subsystems.
  • Design CPU cores, cache subsystems, MMUs, interconnects, and system controllers using Verilog/SystemVerilog.
  • Optimize designs for performance, power, area, latency, throughput, and scalability.
  • Lead processor design initiatives, conduct architecture and RTL reviews, and establish design guidelines.
  • Collaborate with architecture, verification, physical design, DFT, firmware, and software teams.
  • Support synthesis, timing closure, low-power implementation, silicon bring-up, debug, characterization, and production ramp.

Requirements

  • Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field.
  • 12+ years of experience in processor, CPU, DSP, or complex SoC digital design.
  • Deep knowledge of processor microarchitecture, including pipelines, caches, branch prediction, memory hierarchy, MMU/TLB design, interrupts, exceptions, and coherency protocols.
  • Expert-level Verilog/SystemVerilog RTL design experience.
  • Strong knowledge of synthesis, timing analysis, CDC, RDC, low-power design, and industry-standard EDA flows.
  • Strong debugging and problem-solving skills.

Nice to have

  • Experience with RISC-V, ARM, MIPS, ARC, or custom CPU architectures.
  • Knowledge of multicore and heterogeneous computing systems.
  • Experience with AI/ML acceleration, vector processing, performance modeling, or architectural simulation.
  • Silicon bring-up and post-silicon debug experience.
  • Exposure to safety-critical design standards such as ISO 26262 or DO-254.

Culture & Benefits

  • Full-time employment with hirify.global.
  • Commitment to equal opportunity and workplace diversity.
  • Environmental, health, safety, and security programs are part of the work environment.
  • Reasonable accommodations are available during the employment process.

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