Semiconductor Package Development Engineer (Quantum Computing)

Location: Tokyo, Japan; hybrid workplace

Company

hirify.global engineers scalable quantum computers designed to address challenging problems in healthcare, advanced materials, aerospace, and other fields.

What you will do

• Initiate packaging concepts and drive advanced IC package development using ceramic package technology for next-generation quantum microchips.
• Develop package methodology, innovations, and productivity improvements internally and with external suppliers.
• Develop packages for silicon testing in extreme environments, including cryogenic and low-vacuum conditions.
• Apply package design, layout, CAD, thermo-mechanical simulation, and FEM modelling across thermal, electrical, and mechanical requirements.
• Lead electro-mechanical packaging tests and resolve reliability issues across a wide temperature range.

Requirements

• Business-level Japanese and English required for technical discussions, documentation, and supplier interactions.
• Senior expertise or a PhD in mechanical engineering, materials science, physics, packaging, micro/nanofabrication, or a related field.
• Experience with semiconductor package design, layout, assembly manufacturing, micro-assembly techniques, and materials processing.
• Experience using CAD tools, thermo-mechanical simulation, and FEM for thermal, electrical, and mechanical analysis.
• Knowledge of package reliability, failure mechanisms, mechanical and thermal stresses, and Design for X principles.
• Experience with electro-mechanical testing methodology for IC packaging and strong engineering problem-solving fundamentals.

Nice to have

• Knowledge of Through Silicon Via, silicon processing, and thin-film processing.
• Experience with 2.5D/3D packaging, cryogenic electro-mechanical testing, or low-outgassing and ultra-high-vacuum compatibility.
• Experience with high-voltage or power package qualification, process engineering, or advanced package assembly.