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2 дня назад

Senior RTL Design Engineer (AI Accelerators)

120 000 - 200 000$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Senior RTL Design Engineer (AI Accelerators) (SystemVerilog/ASIC): Designing compute datapath, on-chip network, and memory subsystem blocks for RDU AI accelerator ASICs with an accent on microarchitecture, high-performance RTL, and PPA trade-offs. Focus on carrying designs through synthesis, timing closure, tape-out, and silicon bring-up while collaborating with architecture, verification, and physical design teams.

Location: Austin, Texas, United States, or San Jose, California, United States

Salary: $120,000–$200,000 USD base salary per year

Company

Builds a full-stack generative AI platform spanning the SN40L AI accelerator chip, models, and cloud or on-premises deployment.

What you will do

  • Design component units and own RTL blocks within Reconfigurable Dataflow Unit AI accelerator ASIC subsystems.
  • Contribute to microarchitecture specifications and implement and debug high-performance SystemVerilog RTL.
  • Carry designs through synthesis, implementation, tape-out, and silicon bring-up.
  • Make power, performance, and area trade-offs for compute datapath, on-chip network, and memory subsystem designs.
  • Collaborate with principal engineers, architects, design verification, and physical design teams.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • 5+ years of ASIC RTL design experience.
  • Strong knowledge of computer architecture, digital logic design, and SystemVerilog RTL for high-speed ASICs.
  • Experience with AXI, PCIe, Ethernet, HBM or DDR, synthesis, and static timing analysis.
  • Proficiency with linting, clock domain crossing, logical equivalence checking, SystemVerilog Assertions, and hardware performance analysis tools.
  • Python and Linux shell scripting skills, plus familiarity with Git.

Nice to have

  • Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science.
  • Experience with a full ASIC development cycle through tape-out and production silicon.
  • Knowledge of AI workload acceleration and low-power techniques such as clock gating and DVFS.
  • Experience with emulation or FPGA prototyping for pre-silicon validation.

Culture & Benefits

  • Work on a full-stack generative AI platform and custom AI accelerator architecture.
  • US-based full-time employment includes equity and comprehensive benefits.
  • Medical insurance covers 95% of employee premiums and 77% of dependent premiums, with an employer-contributed HSA.
  • Dental, vision, disability, life, AD&D, and flexible spending account options are available.
  • Well-being benefits include Headspace, Gympass+, One Medical, and counseling services.

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