Lead RTL Design Engineer (IoT/AI)

Location: Austin, Texas; Pittsburgh, Pennsylvania; or San Jose, California

Salary: $160,000–$250,000 per year, plus equity and benefits

Company

hirify.global is developing an energy-efficient general-purpose processor for continuous AI/ML workloads in IoT devices and edge computing applications.

What you will do

• Own processor and compute-unit microarchitecture, including dataflow pipelines, execution units, interfaces, and performance, power, and area targets.
• Define on-chip interconnects, data movement, memory interfaces, ordering, synchronization, and scalable system architecture.
• Lead configuration, scheduling, and execution models for multi-kernel workloads and host-system interaction.
• Drive clocking, reset, power-domain, retention, and other low-power strategies for energy-efficient SoC designs.
• Collaborate with compiler, software, architecture, design verification, and physical design teams on hardware/software co-design.
• Support synthesis, PPA analysis, verification planning, DFT, tape-out, silicon bring-up, and lab debug.

Requirements

• 8+ years of RTL design experience, including tape-out ownership of dataflow designs, on-chip networks, memory subsystems, or peripheral integration for processor or accelerator SoCs.
• Deep SystemVerilog expertise with synthesis-clean, lint-clean, timing-aware RTL, including state machines, arbiters, token-flow controllers, and datapath logic.
• Strong understanding of dataflow, SIMD, or systolic-array execution models and producer-consumer synchronization.
• Experience with SRAM wrappers, scratchpad or TCM memory, banking, memory-mapped registers, and at least one standard bus protocol such as AXI, AHB, APB, TileLink, or an equivalent NoC protocol.
• Experience with UPF-driven low-power flows, clock gating, power domains, retention registers, AON wakeup logic, synthesis, timing closure, SDC constraints, STA reports, and QoR analysis.
• Ability to write microarchitecture specifications and design-review materials independently, plus experience with memory compiler toolchains.

Nice to have

• RTL ownership of a dataflow engine, NPU, or streaming DSP architecture with explicit token management.
• Compiler or graph-optimization collaboration, including graph IR, ONNX, or TFLite integration.
• NVM controller RTL experience with MRAM or RRAM, ECC, program/erase sequencing, and model-weight storage.
• Experience with IoT power budgets, functional safety standards, formal verification, deadlock freedom, or bus protocol compliance.
• Tape-out experience on edge-AI, IoT, or wearable SoCs at 12nm or below.

Culture & Benefits

• Meaningful equity program and competitive compensation.
• 401(k) match and company-paid benefits.
• Paid parental leave and workplace flexibility.
• Opportunities for personal and professional development within a newly formed hardware engineering organization.