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9 часов назад

Member of Technical Staff, Hardware, RTL Design Engineer (AI)

200 000 - 420 000$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Member of Technical Staff, Hardware, RTL Design Engineer (AI): Architecting and implementing high-performance custom silicon for AI accelerators and related SoC components with an accent on RTL design, micro-architecture, physical design integration, and performance optimization. Focus on building power-efficient SystemVerilog datapaths, resolving timing violations, and co-designing hardware with compiler, performance modeling, verification, and software teams.

Location: Based in Austin, Texas or Palo Alto, California

Annual salary: $200,000–$420,000 USD, depending on background, skills, and experience.

Company

hirify.global is building personal AI systems spanning local-inference hardware, custom training infrastructure, user interfaces, and deep learning research.

What you will do

  • Define architectures and detailed micro-architectures for AI hardware subsystems.
  • Design complex RTL in SystemVerilog, including pipelines and power-efficient data paths.
  • Collaborate with backend teams on synthesis, floorplanning, power analysis, and physical design integration.
  • Drive static timing analysis and resolve timing violations to meet target frequencies.
  • Work with compiler, performance modeling, software, verification, and physical design teams to identify and resolve system bottlenecks.
  • Own major portions of custom silicon from design through functional and performance validation.

Requirements

  • Bachelor’s degree in Electrical Engineering or Computer Engineering and 5+ years of practical industry experience with advanced process nodes at 7nm or below.
  • Expertise with industry-standard RTL, synthesis, physical design, and timing tools, including SystemVerilog, VCS/Verdi, Fusion Compiler, and PrimeTime.
  • Expert knowledge of computer architecture for at least one chip type, such as SoCs, CPUs, GPUs, or AI accelerators.
  • Proven delivery of functional, performant silicon, including ECO experience and reliable silicon at scale.
  • Collaborative approach to hardware co-design with adjacent engineering teams.
  • Visa sponsorship is available; the role is based in the United States.

Nice to have

  • Post-silicon bug fixing, firmware patching, and low-level GPIO, I2C, SPI, or UART debugging.
  • C, C++, Python, and ISA assembly experience for debugging performance models and kernels.
  • Experience with PCIe, UCIe, HBM, or DDR memory controllers.
  • Knowledge of NoC communication protocols such as AXI, CHI, or credit-based and valid/ready protocols.

Culture & Benefits

  • Health, dental, and vision benefits.
  • Unlimited paid time off.
  • Relocation support as needed.
  • Collaboration with scientists, engineers, and builders working across hardware, software, and AI research.

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