1 день назад
Member of Technical Staff, Hardware, Design Verification Engineer
200 000 - 420 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Member of Technical Staff, Hardware, Design Verification Engineer (SystemVerilog/UVM): Verifying high-performance custom silicon by building scalable test environments across simulation, formal verification, and emulation with an accent on architectural coverage, constrained-random testing, and functional correctness. Focus on developing UVM infrastructure, proving critical logic with SVA, debugging RTL failures, and automating regression flows for complex AI accelerators or SoCs.
Location: Austin, Texas or Palo Alto, California, United States
Annual salary: $200,000–$420,000 USD
Company
is building personal AI systems spanning local-inference hardware, training infrastructure, user interfaces, and deep learning research.
What you will do
- Define verification strategies and plans from architectural and micro-architectural specifications.
- Build scalable, reusable SystemVerilog and UVM test benches with agents, scoreboards, drivers, monitors, and predictors.
- Develop constrained-random sequences, functional coverage models, and code coverage analysis.
- Apply formal verification methods, including SVA and property checking, to validate critical logic.
- Use ZeBu, HAPS, Palladium, and Protium platforms for emulation and prototyping.
- Debug waveform failures, resolve functional issues with RTL designers, and automate regression flows using Python, Perl, Bash, or TCL.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science and 5+ years of industry experience.
- Deep hands-on experience building UVM-based verification environments.
- Expertise in SystemVerilog, object-oriented programming, randomization, and functional coverage.
- Strong understanding of pipelines, cache coherency, memory consistency models, and high-speed interconnects such as AXI and CHI.
- Experience verifying high-performance silicon, including CPUs, GPUs, AI accelerators, or complex SoCs.
- Collaborative approach to working with RTL design, performance modeling, verification, and compiler teams.
Nice to have
- Experience with SVA and formal tools such as Jasper or VC Formal.
- Understanding of emulation and prototyping environments.
- Post-silicon bring-up, testing, and debugging experience.
- Experience with CI/CD, regression management, EDA tools, and verification infrastructure.
Culture & Benefits
- Visa sponsorship is available, subject to role and candidate fit.
- Relocation support is available as needed.
- Health, dental, and vision benefits.
- Unlimited paid time off.
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