Senior Technical Staff Engineer - Analog Design

Location: Montreal, Canada

Company

hirify.global develops semiconductor products and solutions for technologies used around the world, including next-generation timing and communication systems.

What you will do

• Define architectures, specifications, and design methodologies for high-performance analog and mixed-signal IP.
• Develop IP for PLLs, DLLs, ADCs, DACs, filters, high-speed I/O interfaces, and related timing circuits.
• Lead top-level mixed-signal system architecture and integrate analog IP into complex SoC environments.
• Lead transistor-level design, process-corner simulations, behavioral modeling, and Verilog-A development.
• Guide silicon bring-up, validation, characterization, test planning, and laboratory evaluation.
• Provide technical leadership and mentorship through design reviews and collaboration with architecture, digital, layout, product, and multi-site engineering teams.

Requirements

• Master’s degree or Doctorate in Electrical Engineering or a closely related field.
• 10+ years of industry experience in analog and mixed-signal IC design.
• Proven experience designing PLLs, DLLs, ADCs, DACs, filters, and high-speed I/O circuits.
• Strong fundamentals in device physics, circuit theory, and layout-aware design.
• Extensive experience with Cadence IC design tools and flows.
• Hands-on experience with scripting and automation using Skill, Python, Perl, or Tcl, plus strong communication skills in multi-site engineering environments.

Nice to have

• Advanced academic study or research in analog or mixed-signal design.
• Experience applying research concepts to production-ready silicon.
• Expertise in mixed-signal system-level design and architecture.
• Advanced Verilog-A proficiency and experience with silicon bring-up, debugging, and laboratory characterization.
• Exposure to MEMS analog interface circuits.

Culture & Benefits

• Technically rigorous and stable engineering environment.
• Opportunities to influence long-term product direction and mentor designers.
• Emphasis on disciplined engineering, collaboration, and reliable product delivery.
• Travel requirement of 0%–25%.