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7 часов Π½Π°Π·Π°Π΄

Sr Principal Digital Design Engineer (ASIC)

184Β 400 - 272Β 950$
Π€ΠΎΡ€ΠΌΠ°Ρ‚ Ρ€Π°Π±ΠΎΡ‚Ρ‹
onsite
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
senior
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
US
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
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TL;DR

Sr Principal Digital Design Engineer (ASIC): Leading the design and implementation of complex micro-architecture and RTL for custom silicon solutions with an accent on high-performance AI and XPU compute platforms. Focus on building a world-class design team in San Diego, establishing technical methodology, and driving end-to-end development from micro-architecture to silicon bring-up.

Location: Onsite in San Diego, CA. This role requires eligibility to access export-controlled information under U.S. law.

Salary: $184,400–$272,950 per annum.

Company

hirify.global is a global leader in semiconductor solutions, providing the essential building blocks for data infrastructure across cloud, AI, and enterprise architectures.

What you will do

  • Design, implement, and verify micro-architecture and RTL for complex power management integrated circuits.
  • Collaborate with system and chip architects to deliver industrial-quality implementations.
  • Manage the full design development cycle, including test plan reviews, silicon bring-up, and IP maintenance.
  • Produce comprehensive block micro-architecture and register specifications.
  • Supervise and mentor digital design engineers while establishing design and verification methodologies.
  • Lead cross-functional technical reviews to ensure high-quality project delivery.

Requirements

  • Bachelor’s degree with 15+ years, Master’s with 10-12+ years, or PhD with 8-10+ years of professional experience.
  • Must be eligible to access export-controlled information under U.S. export control laws.
  • Expertise in SystemVerilog RTL coding, high-speed design, and multiple clock domains.
  • Deep knowledge of PCIe, CXL, AXI, DDR, and Ethernet protocols.
  • Proficiency in synthesis, static-timing closure, formal verification, and gate-level simulations.
  • Strong leadership skills with the ability to define culture and technical strategy from the ground up.

Nice to have

  • Experience designing high-speed (>1 GHz) embedded processor SoC products.
  • Proficiency in scripting languages such as Python, Perl, or Tcl.
  • Experience with SVA assertions and advanced formal verification tools.

Culture & Benefits

  • Comprehensive financial well-being programs including an employee stock purchase plan with a 2-year look back.
  • Robust family support and work-life balance initiatives.
  • Extensive mental and physical health resources.
  • Recognition and service awards to celebrate professional milestones.
  • Opportunity to shape the technical DNA of a new strategic design center.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’