Sr Principal Digital Design Engineer (ASIC)
ΠΡΡΡ & Π‘ΠΎΠΏΡΠΎΠ²ΠΎΠ΄
ΠΠ»Ρ ΠΌΡΡΡΠ° Ρ ΡΡΠΎΠΉ Π²Π°ΠΊΠ°Π½ΡΠΈΠ΅ΠΉ Π½ΡΠΆΠ΅Π½ Plus
ΠΠΏΠΈΡΠ°Π½ΠΈΠ΅ Π²Π°ΠΊΠ°Π½ΡΠΈΠΈ
TL;DR
Sr Principal Digital Design Engineer (ASIC): Leading the design and implementation of complex micro-architecture and RTL for custom silicon solutions with an accent on high-performance AI and XPU compute platforms. Focus on building a world-class design team in San Diego, establishing technical methodology, and driving end-to-end development from micro-architecture to silicon bring-up.
Location: Onsite in San Diego, CA. This role requires eligibility to access export-controlled information under U.S. law.
Salary: $184,400β$272,950 per annum.
Company
is a global leader in semiconductor solutions, providing the essential building blocks for data infrastructure across cloud, AI, and enterprise architectures.
What you will do
- Design, implement, and verify micro-architecture and RTL for complex power management integrated circuits.
- Collaborate with system and chip architects to deliver industrial-quality implementations.
- Manage the full design development cycle, including test plan reviews, silicon bring-up, and IP maintenance.
- Produce comprehensive block micro-architecture and register specifications.
- Supervise and mentor digital design engineers while establishing design and verification methodologies.
- Lead cross-functional technical reviews to ensure high-quality project delivery.
Requirements
- Bachelorβs degree with 15+ years, Masterβs with 10-12+ years, or PhD with 8-10+ years of professional experience.
- Must be eligible to access export-controlled information under U.S. export control laws.
- Expertise in SystemVerilog RTL coding, high-speed design, and multiple clock domains.
- Deep knowledge of PCIe, CXL, AXI, DDR, and Ethernet protocols.
- Proficiency in synthesis, static-timing closure, formal verification, and gate-level simulations.
- Strong leadership skills with the ability to define culture and technical strategy from the ground up.
Nice to have
- Experience designing high-speed (>1 GHz) embedded processor SoC products.
- Proficiency in scripting languages such as Python, Perl, or Tcl.
- Experience with SVA assertions and advanced formal verification tools.
Culture & Benefits
- Comprehensive financial well-being programs including an employee stock purchase plan with a 2-year look back.
- Robust family support and work-life balance initiatives.
- Extensive mental and physical health resources.
- Recognition and service awards to celebrate professional milestones.
- Opportunity to shape the technical DNA of a new strategic design center.
ΠΡΠ΄ΡΡΠ΅ ΠΎΡΡΠΎΡΠΎΠΆΠ½Ρ: Π΅ΡΠ»ΠΈ ΡΠ°Π±ΠΎΡΠΎΠ΄Π°ΡΠ΅Π»Ρ ΠΏΡΠΎΡΠΈΡ Π²ΠΎΠΉΡΠΈ Π² ΠΈΡ ΡΠΈΡΡΠ΅ΠΌΡ, ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΡ iCloud/Google, ΠΏΡΠΈΡΠ»Π°ΡΡ ΠΊΠΎΠ΄/ΠΏΠ°ΡΠΎΠ»Ρ, Π·Π°ΠΏΡΡΡΠΈΡΡ ΠΊΠΎΠ΄/ΠΠ, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡΠ΅ ΡΡΠΎΠ³ΠΎ - ΡΡΠΎ ΠΌΠΎΡΠ΅Π½Π½ΠΈΠΊΠΈ. ΠΠ±ΡΠ·Π°ΡΠ΅Π»ΡΠ½ΠΎ ΠΆΠΌΠΈΡΠ΅ "ΠΠΎΠΆΠ°Π»ΠΎΠ²Π°ΡΡΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡΠΈΡΠ΅ Π² ΠΏΠΎΠ΄Π΄Π΅ΡΠΆΠΊΡ. ΠΠΎΠ΄ΡΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β