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7 дней назад

Senior Advanced Packaging Engineer (AI)

Формат работы
remote (только Taiwan)
Тип работы
fulltime
Грейд
senior
Английский
c1
Страна
Taiwan
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
Senior Advanced Packaging Engineer (AI): Developing and qualifying CoWoS-based, multi-die chiplet packaging for next-generation AI and high-performance computing products with an accent on package integration, manufacturing readiness, and yield improvement. Focus on coordinating foundry, substrate, and system assembly partners in Taiwan, resolving package and process issues, and driving qualification through production ramp.

Location: Remote, Taiwan (HSQ)

Company

hirify.global is a Silicon Valley-based hardware startup developing infrastructure solutions that accelerate AI data centers through innovations in silicon, packaging, software, and systems.

What you will do

  • Plan and execute test vehicles for advanced packaging process development, material evaluation, design validation, and manufacturing readiness.
  • Coordinate package development, engineering builds, qualification milestones, tooling, materials, process maturity, and yield performance with foundries, substrate suppliers, OSATs, and system assembly partners.
  • Serve as the primary local technical interface with external engineering and manufacturing partners in Taiwan.
  • Lead resolution of package integration, manufacturing, quality, yield, material, and build issues through root cause analysis and corrective actions.
  • Ensure packaging solutions satisfy DFM, thermal, mechanical, electrical, reliability, and system-level requirements.
  • Report technical status, risks, recommendations, qualification results, and manufacturing readiness to US-based engineering leadership and global stakeholders.

Requirements

  • Bachelor’s degree in Mechanical Engineering, Electrical Engineering, Chemical Engineering, Materials Science, or a related engineering discipline.
  • 8+ years of hands-on experience in advanced semiconductor packaging, including multi-die integration, CoWoS, silicon interposers, silicon bridges, or comparable chiplet packaging technologies.
  • Experience planning, developing, and qualifying engineering test vehicles for package technology development, process optimization, and product enablement.
  • Strong knowledge of advanced substrates, silicon interposers, die-to-die interconnects, fine-pitch assembly, multi-chip packages, and package or board-level reliability testing.
  • Working knowledge of DFM, DOE, FMEA, root cause analysis, failure analysis, and process qualification methodologies.
  • Fluent Mandarin and English with excellent written and verbal communication skills; ability to build relationships with packaging and system assembly partners in Taiwan.

Nice to have

  • Master’s degree in a relevant engineering or materials discipline.

Culture & Benefits

  • Work independently in a fast-paced product development environment.
  • Collaborate with global cross-functional engineering teams and international supply-chain partners.
  • Join a world-class engineering organization working on AI data-center infrastructure and next-generation semiconductor packaging.

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