IC Design Engineer (ASIC)

Location: Cambridge, England, United Kingdom; full-time office attendance required.

Company

hirify.global develops its own silicon, including the RP2040 microcontroller, RP1 southbridge chip, and RP2350 second-generation microcontroller.

What you will do

• Own front-end ASIC tasks from specification through design, verification, and implementation.
• Design and integrate IP, and plan and execute verification.
• Specify and configure IP and complete systems.
• Work closely with the software team and support FPGA platforms for software development and verification.
• Assist the implementation team with power and timing issues.

Requirements

• Typically 10+ years of experience in SoC or MCU architecture, including at least one tape-out with architectural ownership of a chip or non-trivial subsystem.
• Deep understanding of microcontroller and processor design, including real-time behaviour, deterministic interrupt handling, low-power modes, flash/SRAM hierarchies, and peripherals such as SPI, I²C, UART, USB, PIO-style fabrics, ADC/DAC, and timers.
• Strong understanding of SoC concepts, including coherent and non-coherent interconnect, AXI/AHB/APB, cache hierarchies, DMA, memory controllers, security architecture such as TrustZone or equivalent, and coexistence of OS-class subsystems with real-time domains.
• Credible knowledge across RTL using SystemVerilog, verification methodologies including UVM, formal, and emulation/FPGA, DFT, timing closure, power analysis, and physical design constraints.
• Experience making engineering trade-offs under cost, schedule, and PPA pressure and communicating them clearly to engineers and non-engineers.
• Experience writing non-trivial embedded C, understanding toolchain and SDK implications, and considering the developer experience of shipped chips.
• Ability to communicate complex ideas, design goals, and status verbally and through documentation.
• Strong drive and ability to work to a schedule.
• Familiarity with scripting languages such as Bash, Python, or Tcl.

Nice to have

• Experience with the Cadence simulation tool flow.
• Experience with ASIC/FPGA synthesis and implementation, DFT architecture and insertion, software development, and scripting.

Culture & Benefits

• Work in a small ASIC team involved across the silicon flow, from specification through production.
• Competitive salary based on experience level.
• Employer pension contribution of 8% when contributing 4% of gross salary through the salary sacrifice scheme.
• Life assurance of four times base salary, income protection at 75% of base salary, and private medical insurance.
• Access to an electric vehicle salary sacrifice scheme subject to eligibility.