Physical Design Engineer

Location: On-site in New York City, Silicon Valley, Copenhagen, London, or Zurich

Salary: $200,000–$400,000 per year plus equity

Company

hirify.global is an applied AI company developing foundational hardware and software for the semiconductor industry, AI infrastructure, and advanced computing systems.

What you will do

• Own the complete netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, CTS, and P&R.
• Perform STA, create and validate timing constraints, and drive timing closure across operating corners and modes.
• Optimize power, performance, and area while analyzing power integrity, IR/EM effects, and crosstalk.
• Execute DRC, LVS, ERC, antenna, and other physical signoff checks for chip and block designs.
• Collaborate with RTL, architecture, and DFT teams on macro placement, pin assignments, floorplanning, and physical feasibility.
• Manage tapeout checklists and stream-out, and support post-silicon physical debugging and bring-up.

Requirements

• At least 3 successful tapeouts from netlist to signoff, ideally on advanced technology nodes.
• Deep hands-on experience with physical design tools such as Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, or Calibre.
• Strong debugging skills for STA bottlenecks, IR/EM issues, crosstalk, and DRC/LVS violations.
• Ability to work cross-functionally with RTL, architecture, and DFT teams on early physical feasibility.
• Meticulous execution and experience taking complex architectures through physical signoff.

Nice to have

• Experience at an AI or HPC chip startup with tightly integrated design, verification, and physical design cycles.
• Experience with custom memory or macro floorplanning, hierarchical top-level implementation, or chiplets and 2.5D/3D integration.
• Experience developing or maintaining automated TCL or Python frameworks for physical design flows.

Culture & Benefits

• Work as part of a cross-functional engineering organization spanning multiple international locations.
• Collaborate with advanced institutions on AI, silicon, and computing infrastructure.
• Full-time employment with equity participation.
• Inclusive equal-opportunity workplace with reasonable accessibility accommodations.