Advanced Packaging Architect

Location: On-site in Austin, Texas, United States; Bristol, United Kingdom; or London, United Kingdom.

Company

hirify.global develops the hirify.global Decode Accelerator 1 (DX-1), a rack-scale AI decode accelerator based on co-designed logic, data movement, packaging, optics, and interconnect.

What you will do

• Own package architecture and design for ASIC-to-substrate integration, including bump and pad mapping, substrate escape, interconnect strategy, floorplanning, and stack-up definition.
• Lead the full package design flow from concept and detailed design through simulation, layout, verification, release, manufacturing support, and product readiness.
• Develop future 2.5D and 3D architectures with multi-die, chiplet-style, heterogeneous, and optical integration approaches.
• Direct package-level signal integrity and power integrity analysis, translating simulation results into design improvements and sign-off decisions.
• Establish packaging methodologies, libraries, templates, design rules, tool flows, and workflows across package, substrate, simulation, and PCB environments.
• Collaborate with ASIC, optics, mechanical, thermal, systems, substrate, OSAT, foundry, and manufacturing partners through qualification, bring-up, production, and issue resolution.

Requirements

• 10+ years of experience in advanced semiconductor packaging for ASIC or other high-performance products.
• Demonstrated ownership of packaging architecture, technology strategy, or roadmap development for complex products.
• Deep expertise in front-end package design, including ASIC-to-substrate integration, package structures, interconnect technologies, manufacturability, and reliability.
• Strong experience with 2.5D and/or 3D package architectures, including multi-die and heterogeneous integration.
• Strong hands-on experience with package design tools such as Cadence Allegro X APD, Siemens Xpedition, or equivalent.
• Experience leading package development across layout, simulation, verification, and release, including package-level signal integrity and power delivery analysis with Ansys SIwave, Cadence Sigrity, or equivalent.
• Experience in substrate design and package-to-board integration.
• Experience building packaging capabilities, processes, or teams, or leading engineers while remaining a hands-on contributor.
• Strong working relationships with substrate vendors, OSATs, and foundry packaging organizations; strong technical judgment, communication, and problem-solving skills.
• Degree in a relevant engineering or physical sciences discipline.

Nice to have

• Experience with AI accelerators, high-performance computing, networking, or advanced data-center hardware.
• Familiarity with wafer-level packaging and emerging advanced packaging platforms.
• Exposure to optical or photonic integration with electronic packaging.
• Familiarity with package reliability, qualification, and failure-analysis workflows.
• Exposure to new product introduction and scaling advanced package technologies into production.

Culture & Benefits

• On-site work in Austin, Bristol, or London.
• Competitive salary based on experience, skills, and location.
• Meaningful stock options and ownership participation.
• Annual Living-Local Bonus for residence within 20 minutes of the office.