1 день назад
Senior Heterogenous Integration Process Engineer
12 380 602 - 17 494 555$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Heterogenous Integration Process Engineer (Semiconductor 3D Integration): Leading R&D programs for heterogeneous and 3D device integration, including wafer bonding, C2W, D2W, and advanced packaging, with an accent on process development, hardware solutions, and technology pathfinding. Focus on evaluating feasibility through modeling, simulation, and experimentation, defining technical strategy, and leading cross-functional programs for next-generation semiconductor manufacturing.
Location: Albany, NY, United States; onsite office-based role
Salary: $123,806.02–$174,945.55 per year
Company
’s TEL Technology Center, America is an advanced R&D center developing semiconductor process technologies and equipment solutions in collaboration with customers, research institutions, and global R&D teams.
What you will do
- Lead R&D programs in heterogeneous and 3D device integration, including C2W, D2W, wafer bonding, fusion bonding, hybrid bonding, wafer thinning, and TSV technologies.
- Define technical strategy and align research activities with business objectives and semiconductor technology roadmaps.
- Conduct fundamental research and develop innovative semiconductor processes and hardware solutions.
- Evaluate technology feasibility through modeling, simulation, and experimentation, and drive technology pathfinding.
- Collaborate with global teams, customers, and joint development partners on technical programs.
- Provide technical leadership, mentor researchers, and communicate results and recommendations to stakeholders.
Requirements
- Ph.D. in materials science, mechanical, chemical, or electrical engineering, physics, chemistry, nanotechnology, or a related field.
- At least 5 years of semiconductor R&D experience.
- Strong expertise in advanced packaging, heterogeneous integration, and/or 3D device integration.
- Hands-on experience with wafer bonding, process integration, or related semiconductor technologies.
- Strong problem-solving, analytical, experimental, project management, organizational, and communication skills.
- Demonstrated technical leadership through cross-functional programs, publications, patents, or industry contributions.
Nice to have
- Experience with bonded-CFET, VCT DRAM, or 3D-stacked memory and logic devices.
- Knowledge of semiconductor industry trends and technology roadmaps.
Culture & Benefits
- Medical, vision, and dental insurance.
- Paid personal leave and holiday time.
- 401(k) retirement plan with employer matching.
- Tuition reimbursement and healthy lifestyle incentives.
- Employee assistance programs.
- Travel of up to 20% may be required.
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