Назад
Company hidden
обновлено 9 дней назад

3D Heterogeneous Integration Design Enablement Engineer (2026 New College Graduate)

65 400 - 145 800$
Формат работы
onsite
Тип работы
fulltime
Грейд
junior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
3D Heterogeneous Integration Design Enablement Engineer (2026 New College Graduate) (advanced packaging/semiconductor manufacturing): Developing design enablement specifications, design manuals, test vehicles, and PDK requirements for 3D heterogeneous integration with an accent on wafer bonding, TSV/TOV, interposers, and manufacturability rules. Focus on translating packaging requirements into device enablement specifications, coordinating tapeout and mask reviews, and collaborating with R&D, fab teams, vendors, OSATs, and customers.

Location: Malta, New York, USA

Salary: $65,400–$145,800 per year

Company

hirify.global is a full-service semiconductor foundry providing design, development, and fabrication services with manufacturing operations across three continents.

What you will do

  • Develop 3D heterogeneous integration design enablement for advanced packaging R&D, including wafer-to-wafer bonding, die-to-wafer bonding, TSV/TOV, and interposer development.
  • Publish Design Manual specifications based on packaging failure modes and product-line requirements.
  • Translate advanced packaging requirements into device enablement specifications covering design rules, TSV layouts, LVS requirements, and device model terminals.
  • Draft test vehicle content and test specifications, and support tapeout and mask review activities.
  • Coordinate with inline and laboratory test teams, vendors, OSATs, product lines, fab teams, and customers.
  • Support environmental, health, safety, and security requirements and other assigned engineering activities.

Requirements

  • PhD with a completed defended thesis or a master’s degree in Electrical Engineering, Materials Science, or a related field.
  • Minimum overall GPA of 3.0 and good academic standing.
  • Fluent written and verbal English required.
  • Availability to travel up to 10%.
  • Ability to work onsite in Malta, New York.

Nice to have

  • Internship or co-op experience in design or EDA/design enablement.
  • Knowledge of semiconductor packaging process modules and integration.
  • Leadership experience in workplace, academic projects, or competitions.
  • Project management, planning, organizational, written, and verbal communication skills.

Culture & Benefits

  • Full-time employment at a semiconductor manufacturing and R&D organization.
  • Work in a state-of-the-art 300mm fabrication facility.
  • Equal opportunity workplace with a focus on cultural diversity.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →