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16 часов назад

3D Heterogeneous Integration Design Enablement Engineer (2026 New College Graduate)

79 100 - 145 800$
Формат работы
onsite
Тип работы
fulltime
Грейд
trainee
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
3D Heterogeneous Integration Design Enablement Engineer (2026 New College Graduate) (3D heterogeneous integration and advanced packaging): Developing design enablement specifications for next-generation packaging R&D, including wafer-to-wafer bonding, die-to-wafer bonding, TSV/TOV, and interposer development with an accent on design rules, PDK requirements, and manufacturability. Focus on drafting design manuals and test vehicle specifications, coordinating tapeout and mask reviews, and aligning packaging requirements with process, test, product, fab, vendor, OSAT, and customer teams.

Location: USA - New York - Malta

Salary: $79,100–$145,800 per year, depending on qualifications, experience, and location.

Company

hirify.global is a full-service semiconductor foundry providing design, development, and fabrication services with a global manufacturing footprint.

What you will do

  • Develop 3D heterogeneous integration design enablement for advanced packaging R&D, including wafer-to-wafer bonding, die-to-wafer bonding, TSV/TOV, and interposer development.
  • Publish Design Manual specifications based on packaging failure modes in collaboration with unit process and R&D engineers.
  • Translate advanced packaging requirements into device enablement specifications covering design rules, TSV library layouts, LVS requirements, and device model terminals.
  • Draft test vehicle content and test specifications, and support tapeout and mask review activities.
  • Coordinate with inline and laboratory test teams, vendors, and OSATs on test vehicles, masks, and packaging design.
  • Facilitate design interactions between product lines, fab teams, and customers.

Requirements

  • PhD with a completed and defended thesis or a master's degree in Electrical Engineering, Materials Science, or a related field.
  • Overall GPA of at least 3.0 and proven good academic standing.
  • English fluency required for written and verbal communication.
  • Ability to travel up to 10%.
  • Ability to work on advanced packaging design enablement in a semiconductor fabrication environment.

Nice to have

  • Internship or co-op experience in design or EDA/design enablement.
  • Fundamental knowledge of semiconductor packaging process modules and integration.
  • Leadership experience in the workplace, academic projects, or competitions.
  • Project management, communication, planning, and organizational skills.

Culture & Benefits

  • Full-time employment in a 300mm fabrication facility.
  • Commitment to environmental, health, safety, and security programs.
  • Equal opportunity workplace with a focus on diversity and inclusion.
  • Reasonable accommodation available during the employment process upon request.

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