Senior Staff Engineer, SoC Architecture – Memory Subsystem and Interconnect (SoC Architecture)

Location: Onsite office position in Mountain View, California, USA

Hourly pay rate range: $197,800–$296,600 USD

Company

hirify.global develops SoC architecture, bus and memory subsystems, multimedia subsystems, and key IP blocks for future Galaxy smartphones, tablets, and other devices.

What you will do

• Lead architecture and microarchitecture development for fabric, system cache, and DRAM controller subsystems.
• Develop features that improve power and performance across targeted workloads in next-generation SoCs.
• Evaluate architecture proposals using high-level performance modeling, simulation, benchmarks, and complex use cases.
• Deliver architecture and microarchitecture specifications to hardware and software design teams.
• Collaborate with SoC architects, software, hardware, leadership, silicon bring-up, and product teams.
• Verify and debug proposed features and their delivered performance across the SoC, drivers, and operating system.

Requirements

• Bachelor’s, master’s, or PhD in computer science, computer engineering, or equivalent education and experience.
• 12+ years of experience in SoC or ASIC design and architecture.
• More than 9 years of direct experience in fabric, system cache, DRAM controller architecture, or microarchitecture.
• Strong understanding of memory controller architecture, memory scheduling, prioritization, and QoS.
• Detailed knowledge of ARM bus infrastructure, including ACE, AXI, and AHB.
• Knowledge of JEDEC standards such as LPDDR, DDR, or HBM, plus understanding of memory bandwidth, latency, performance, power, and SoC area tradeoffs.

Nice to have

• Experience with BookSim Simulator.
• Experience with Platform Architect.

Culture & Benefits

• Annual bonus eligibility.
• Comprehensive benefits package.
• Inclusive workplace and equal employment opportunity.
• Reasonable accommodations available for qualified individuals with disabilities.