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24 часа назад

Senior Principal Memory Architect (HBM/DDR)

191 530 - 286 900$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Principal Memory Architect (HBM/DDR): Architecting high-performance memory subsystems and controllers for custom compute ASICs serving AI, HPC, and cloud data centers with an accent on performance modeling, micro-architecture, and reliability. Focus on designing ECC and RAS features, optimizing throughput, latency, QoS, power, and area, and collaborating with RTL, physical design, validation, customers, and ecosystem partners.

Location: 100% onsite five days per week in Santa Clara, Irvine, or Boise, United States; no remote or hybrid option

Salary: $191,530–$286,900 per annum

Company

hirify.global develops semiconductor solutions and custom silicon for enterprise, cloud, AI, carrier, and data center infrastructure.

What you will do

  • Architect high-performance HBM and DDR memory subsystems for custom compute products.
  • Develop specifications, performance models, product requirements, and memory controller architecture roadmaps.
  • Drive micro-architecture development, design specifications, and verification plans with RTL, physical design, and validation teams.
  • Build system-level models to optimize throughput, latency, QoS, power, and area across design options.
  • Collaborate with hardware, firmware, validation, customers, and ecosystem partners to ensure product quality, performance, and reliability.
  • Lead memory architecture innovation, including ECC, RAS, and reliability improvements for server-class products.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 15+ years of relevant experience, or a Master’s/PhD with 8+ years of experience in memory architecture or system design.
  • Deep understanding of DDR and HBM memory subsystem architecture for data center compute, AI, or XPU systems.
  • Experience designing or specifying HBM/DDR memory controllers and associated subsystems.
  • Strong familiarity with JEDEC standards, including HBM3/4, DDR4/5, LPDDR5/5X/6, and related memory interface technologies.
  • Experience with system modeling and performance analysis tools, plus ECC, RAS, and reliability features for server or high-performance SoC designs.
  • Applicants must be eligible to access export-controlled technology under U.S. law; an export license review may be required for some applicants.

Culture & Benefits

  • Full-time employment with comprehensive benefits supporting financial well-being, family support, mental health, physical health, and recognition.
  • Employee stock purchase plan with a two-year look back.
  • Family support programs and mental health resources.
  • Recognition and service awards for contributions and milestones.
  • Interviews assess individual experience, thought process, and communication without unauthorized AI assistance.

Hiring process

  • Interview process includes real-time evaluation of experience, reasoning, and communication.
  • Unauthorized AI tools, recording tools, transcription apps, and automated interview assistance are prohibited and may result in disqualification.

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