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Senior Out-of-Order CPU Architect (x86)

190 610 - 361 480$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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TL;DR
Senior Out-of-Order CPU Architect (x86): Defining and developing end-to-end CPU architectures and microarchitectures for high-performance computing and low-power products with an accent on out-of-order pipelines, performance, power, frequency, area, and ISA design. Focus on creating schedulers and execution features, writing RTL in SystemVerilog, converging timing and power across CPU generations, and debugging complex simulation and microarchitecture issues.

Location: Austin, Texas, United States; hybrid work model with time split between the assigned hirify.global site and off-site work

Salary: $190,610–$361,480 USD annual salary

Company

hirify.global's Silicon and Platform Engineering Group develops silicon and platform solutions for current and next-generation computing experiences.

What you will do

  • Define and drive end-to-end CPU architecture specifications based on hardware features, requirements, and lifecycle needs.
  • Set performance, power, frequency, area, and feature targets for CPUs across high-performance and low-power market segments.
  • Develop new microarchitectures, architectural features, instructions, and ISA enhancements for future CPU use cases.
  • Build test plans and infrastructure, simulate functional models, and analyze architecture and feature test results.
  • Collaborate with architecture, design, verification, and validation teams while influencing cross-functional roadmaps.
  • Implement or debug microarchitectural specifications in SystemVerilog when needed to resolve timing and power constraints.

Requirements

  • 15+ consecutive years of experience in high-performance, high-frequency ARM or x86 CPU organizations in design or architecture.
  • 10+ years working on out-of-order CPU pipeline sections, including instruction rename and allocation, schedulers, and execution units.
  • 5+ years writing RTL and owning timing and power convergence across multiple CPU generations.
  • 2+ years building advanced integer or floating-point/vector schedulers.
  • Expertise in CPU architecture fundamentals, microarchitecture design, low-power design, RTL development, and SystemVerilog.
  • Ability to work in the Austin, Texas hybrid role and attend the assigned hirify.global site; the position is also subject to an extended background investigation.

Culture & Benefits

  • Cross-functional collaboration with architects, design, verification, and validation engineers.
  • Competitive compensation with stock bonuses.
  • Health, retirement, and vacation benefits.
  • Hybrid work model combining on-site and off-site work.

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