1 день назад
Senior SoC Chiplet Architect (Chiplet Architecture)
164 470 - 269 100$
Мэтч & Сопровод
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Описание вакансии
Текст:
TL;DR
Senior SoC Chiplet Architect (Chiplet Architecture): Defining multi-generation chiplet-based SoC platforms for networking, hyperscale data center, cloud infrastructure, and AI workloads with an accent on chiplet partitioning, D2D interconnects, system infrastructure, and RAS/security architecture. Focus on evaluating performance, power, area, cost/yield, and software-complexity tradeoffs while aligning architecture, RTL, firmware, software, packaging, and platform teams.
Location: Hybrid work model with on-site and off-site work at sites in Santa Clara, California; Phoenix, Arizona; Folsom, California; Fort Collins, Colorado; Hillsboro, Oregon; or Austin, Texas, United States
Annual salary: $164,470–$269,100 USD
Company
develops semiconductor and computing technologies, including high-performance networking silicon for data centers, cloud infrastructure, and AI workloads.
What you will do
- Define multi-generation chiplet-based SoC architecture strategies, roadmaps, and monolithic-versus-chiplet decision frameworks.
- Lead functional partitioning across compute, networking and I/O, accelerators, memory controllers, security, and management chiplets.
- Architect die-to-die interconnects, bandwidth and latency requirements, reliability mechanisms, flow control, and inter-chiplet QoS.
- Define power, clock, reset, boot, firmware, telemetry, debug, observability, RAS, and security infrastructure across multi-die systems.
- Lead quantitative trade studies covering performance, power, area, cost, yield, schedule, packaging overhead, and product flexibility.
- Align architecture, RTL, design verification, firmware, software, packaging, manufacturing, and platform teams on technical decisions.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related STEM field.
- 7+ years of experience in SoC or system architecture, from requirements definition through silicon execution.
- Experience with multi-die or chiplet partitioning and related D2D, boot/reset, cross-domain QoS, and debug implications.
- Experience leading architecture trade-off studies and communicating decisions to senior technical and business stakeholders.
- Understanding of interconnects and fabrics, memory subsystem behavior, performance modeling, and PPA tradeoffs.
Nice to have
- Familiarity with chiplet interoperability standards and ecosystem discussions.
- Hands-on experience with system bring-up and architecture-driven debug and telemetry planning.
- Experience building or using cost and yield models for architectural decisions.
Culture & Benefits
- Hybrid work model combining on-site work at an assigned site with off-site work.
- Competitive annual compensation, stock bonuses, health benefits, retirement programs, and vacation.
- Opportunity to work across architecture, packaging, manufacturing, firmware, software, and platform organizations.
- Experienced-hire position on a team developing networking platforms for hyperscale data centers, cloud infrastructure, and AI workloads.
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