SoC Memory Subsystem Architect (AI)

Location: Sunnyvale, California, United States; onsite at hirify.global’s Sunnyvale office

Company

hirify.global develops AI silicon and systems, including AI accelerator SoCs.

What you will do

• Provide technical leadership across phases of AI SoC development, primarily designing unified memory space architecture.
• Develop architecture and microarchitecture for SoC fabrics, system caches, system coherency, and MMUs.
• Define and build unified memory space systems across distributed AI training systems with software and SoC design teams.
• Collaborate with hardware design, verification, emulation, and validation teams to build and test architecture, performance, and functionality.
• Simulate features, analyze benchmarks and workloads, and identify microarchitecture optimizations.
• Debug performance and functional issues using high-level models, RTL simulation, and silicon.

Requirements

• 10+ years of experience in silicon architecture or IP design focused on memory subsystems.
• Strong understanding of distributed AI training system requirements for SoC memory subsystems.
• Experience with digital hardware design, CPUs or hardware accelerators, and/or peripheral design.
• Knowledge of software and operating-system requirements for memory systems.
• Experience with system performance analysis and debugging in pre-silicon and/or post-silicon environments.
• Background in system interconnects, system MMUs, caches, memory technologies such as HBM, GDDR, DDR, and LPDDR4/5, data analysis, and a Master’s or PhD in Electrical or Computer Engineering. Excellent communication skills in both English and Chinese are required.

Culture & Benefits

• Work in small, fast-moving teams focused on ambitious AI hardware goals.
• Self-directed environment for motivated professionals.
• Opportunities to learn new skills and grow.
• Collaborative, team-oriented working style.