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42 минуты назад

Senior ASIC Design Engineer (ASIC)

116 150 - 182 400$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior ASIC Design Engineer (Digital ASIC/VLSI): Leading functional blocks and subsystems from RTL design through silicon verification and validation for next-generation HP printer controllers with an accent on embedded systems, ASIC design flows, and hardware–firmware integration. Focus on developing Verilog/SystemVerilog designs, automating Synopsys and Cadence tool flows, prototyping in FPGA models, and resolving complex product integration issues.

Location: Vancouver, Washington, United States of America. Relocation is available.

Salary: $116,150–$182,400 USD annually, with additional bonus and/or equity opportunities for candidates in the United States.

Company

hirify.global develops printing and imaging products, including proprietary ASIC-based controller solutions for enterprise printers.

What you will do

  • Lead digital ASIC functional blocks and subsystems from RTL design through silicon verification, validation, and qualification.
  • Align specifications with internal and external partners, lead design reviews, and complete technical documentation.
  • Manage development-partner relationships and contribute to ASIC roadmaps and future innovation.
  • Lead cross-disciplinary task forces to triage hardware and firmware integration issues.
  • Contribute to Inkjet and LaserJet print architecture, data-path requirements, and FPGA or software-model prototyping.
  • Drive design methodology improvements and tool-flow automation.

Requirements

  • BS or MS degree in electrical engineering or an equivalent qualification, with a focus on VLSI design.
  • 8–10 years of ASIC or SoC design and development experience.
  • Deep knowledge of submicron semiconductor technology and embedded-system design, verification, and product development lifecycles.
  • Experience with digital ASIC/SoC flows from RTL through silicon characterization, including Synopsys and Cadence EDA tools.
  • Proficiency in Verilog, SystemVerilog, Python, Perl, C, and C++, plus code-base management with Subversion, Git, or GitHub.
  • Strong analytical, problem-solving, communication, and negotiation skills, with working knowledge of electronic components, PCA design, and test equipment.

Nice to have

  • Experience with LaserJet printing technology, ARM microprocessor subsystems, or DDR, Flash, and eMMC memory systems.
  • Experience with design database management, scripting, and design-flow automation.
  • Proficiency using AI Copilot and LLM-based tools to accelerate ASIC design and verification.

Culture & Benefits

  • Engineering role within hirify.global’s Imaging & Print organization and Vancouver R&D site.
  • Health, dental, and vision insurance.
  • Short- and long-term disability, life insurance, employee assistance, and flexible spending accounts.
  • 4–12 weeks of fully paid parental leave based on tenure and 11 paid holidays.
  • Flexible paid vacation and sick leave.
  • No travel and no shift premium.

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