FPGA Design Engineer

Location: Hybrid in New York City or Silicon Valley (Mountain View)

Salary: $250,000–$340,000 per year, plus equity

Company

hirify.global is an applied AI company building foundational hardware and software for the semiconductor industry, AI infrastructure, and advanced computing systems.

What you will do

• Lead the selection, procurement, bring-up, and lifecycle ownership of FPGA prototyping platforms for pre-silicon RTL validation and software development.
• Adapt and implement complex ASIC RTL on FPGA targets, including multi-clock-domain architectures, CDC bridges, synthesis, place-and-route, and timing closure.
• Integrate internal designs with third-party and vendor IP using the AMD/Xilinx ecosystem, including Vivado IP Integrator, transceivers, and memory controllers.
• Design and validate high-speed I/O, particularly PCIe interfaces for accelerator cards deployed in standard servers.
• Build FPGA-based tester designs and automated environments for silicon bring-up, device characterization, and post-silicon validation.
• Develop Python and C++ hardware-software tooling, automated build and regression flows, and debug hardware in the lab using FPGA analysis and signal-integrity instruments.

Requirements

• Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware.
• Expert-level SystemVerilog and/or VHDL, with deep proficiency in Xilinx Vivado.
• Hands-on experience implementing and debugging PCIe, AXI/AHB, SPI, UART, JTAG, and related interfaces.
• Strong Python skills for automation, testing, and build tooling.
• Strong board-level bring-up and real-hardware lab debugging skills.
• Ability to work independently and solve ambiguous problems spanning hardware, software, and physics.

Nice to have

• Experience with Cocotb or UVM verification frameworks.
• Experience deploying ML models to FPGAs or building real-time, sub-microsecond signal-processing pipelines.
• Mixed-signal ASIC experience, including digital front-ends and ADC/DAC interfaces.
• SERDES tuning, signal-integrity fundamentals, and hardware CI/CD using GitLab CI or Docker.

Culture & Benefits

• Full-time employment with equity compensation.
• Cross-functional collaboration with silicon, EDA, and research teams.
• Work across offices in New York City, Silicon Valley, London, Copenhagen, and Seoul.
• Inclusive workplace with equal employment opportunity and reasonable accessibility accommodations.