FPGA Design Engineer

Location: Hybrid in New York City or Silicon Valley, United States

Salary: $200,000–$400,000 per year, plus equity

Company

hirify.global is an applied AI company developing foundational hardware and software for the semiconductor industry, AI infrastructure, and advanced computing systems.

What you will do

• Own the selection, procurement, bring-up, and lifecycle of FPGA prototyping platforms for pre-silicon RTL validation and software development.
• Adapt and implement complex ASIC RTL on FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure.
• Integrate internal designs with third-party and vendor IP using the AMD/Xilinx ecosystem, including Vivado IP Integrator, transceivers, and memory controllers.
• Design and validate high-speed I/O, especially PCIe interfaces for accelerator cards in standard servers.
• Build FPGA-based tester designs and automated environments for silicon bring-up, device characterization, and post-silicon validation.
• Develop Python/C++ hardware abstractions, register-map generation, build flows, and regression automation while debugging hardware with lab instrumentation.

Requirements

• Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware, ideally in ASIC prototyping, emulation, or a high-growth hardware environment.
• Expert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado synthesis, place and route, timing closure, and IP integration.
• Hands-on experience implementing and debugging PCIe, AXI/AHB, SPI, UART, JTAG, and other common interfaces.
• Strong Python skills for automation, testing, and build tooling.
• Strong board-level bring-up and real-hardware lab debugging skills, including timing and functional issue analysis.
• Ability to work independently on ambiguous problems spanning hardware, software, and physics.

Nice to have

• Experience with Cocotb or UVM verification frameworks.
• Experience deploying ML models to FPGAs or building real-time, sub-microsecond signal-processing pipelines.
• Mixed-signal ASIC experience, including digital front ends, ADC/DAC interfaces, or analog compute.
• SERDES tuning, signal-integrity fundamentals, and high-speed link characterization.
• Hardware CI/CD experience with GitLab CI or Docker-based build and test systems.

Culture & Benefits

• Full-time employment with competitive, equitable compensation based on role, skills, experience, and location.
• Equity offering.
• Cross-functional collaboration with silicon, EDA, and research teams across New York City, San Francisco, London, Copenhagen, and Pangyo.
• Inclusive workplace committed to equal employment opportunity and reasonable accessibility accommodations.