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17 часов назад

Lead Digital Verification Engineer (ASIC/SoC)

200 000 - 230 000$
Тип работы
fulltime
Грейд
lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Lead Digital Verification Engineer (ASIC/SoC): Defining and executing end-to-end functional verification for complex SoC and IP designs from specification through tapeout with an accent on UVM environments, constrained-random testing, coverage closure, and full-chip validation. Focus on architecting scalable verification infrastructure, debugging multi-block simulation failures, coordinating emulation handoff, and leading verification sign-off for energy-efficient computing products.

Location: San Jose, CA; Pittsburgh, PA; or Austin, TX

Salary: $200,000–$230,000 per year, plus equity and comprehensive benefits.

Company

hirify.global develops energy-efficient general-purpose processors for continuous AI/ML-enabled computing in IoT and edge devices.

What you will do

  • Define end-to-end verification strategies across block, subsystem, and full-chip levels through tapeout.
  • Develop and review verification plans, stimulus strategies, coverage goals, and sign-off criteria.
  • Architect scalable UVM-based testbenches with agents, scoreboards, reference models, assertions, and coverage monitors.
  • Lead constrained-random testing, functional coverage closure, regression optimization, and complex simulation debug.
  • Drive full-chip verification of boot sequences, interrupts, DMA flows, power-on reset, multi-block interactions, CDC, RDC, and multi-power-domain behavior.
  • Lead and mentor the verification team, coordinate with RTL, compiler, DFT, physical design, emulation, and post-silicon teams, and represent verification readiness during tapeout sign-off.

Requirements

  • Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
  • 10+ years of ASIC/SoC design verification experience, including at least 3 years leading verification strategy, sign-off, and team execution.
  • Deep expertise in UVM architecture, constrained-random verification, SystemVerilog classes and constraints, functional coverage, SVA, interfaces, and packages.
  • Experience closing functional and code coverage to tapeout sign-off on complex multi-million-gate SoC or ASIC designs.
  • Strong understanding of processors such as ARM or RISC-V, AMBA AXI/ACE/CHI, memory controllers, DMA engines, interrupt controllers, and standard peripherals.
  • Proficiency in Python, Perl, or Tcl for automation, log analysis, coverage processing, and regression development, plus clear technical communication.

Culture & Benefits

  • Competitive compensation with meaningful equity.
  • 401(k) match and company-paid benefits.
  • Paid parental leave.
  • Flexibility and support for personal and professional development.

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