Experienced Hardware Design Engineer (FPGA/ASIC)

Location: Austin, TX; Boulder, Colorado; Chicago, Illinois; or New York, NY, United States

Salary: USD 200,000–300,000 per year, plus discretionary performance-based bonuses. Compensation may vary by location, skills, knowledge, and experience.

Company

hirify.global applies scientific research and high-performance computing to algorithmic trading across global financial markets.

What you will do

• Develop and deploy custom FPGA and ASIC solutions for trading applications.
• Design efficient hardware implementations for on-the-fly market-data transformations.
• Implement complex data structures and processing models in RTL.
• Investigate new hardware technologies, tools, and vendor tool suites.
• Contribute to the hardware development technology stack in collaboration with cross-functional teams.

Requirements

• At least 2 years of professional RTL design experience for FPGA or ASIC.
• Expert SystemVerilog skills and deep knowledge of FPGA internals or ASIC primitives.
• Ability to describe hardware designs at high, low, and intermediate levels of abstraction.
• Strong design, optimization, debugging, problem-solving, and verification skills.
• Working knowledge of Python and/or C++, and comfort working in a Linux environment.
• Bachelor’s degree in computer science, electrical engineering, or a related field.

Nice to have

• Experience with networking protocols, CPU design, processing pipelines, or machine learning accelerators.
• Familiarity with AMD Vivado.
• Financial industry experience is not required.

Culture & Benefits

• Collaborative, international environment focused on research, automation, and technical innovation.
• Medical, dental, and vision coverage.
• Basic life insurance and retirement savings plans.
• Sick leave, parental leave, 20 vacation days, and 10 paid holidays in the US; policies may vary in other locations.
• AI tools are prohibited during interviews and assessments unless explicitly authorized.