Design Verification (DV) Engineer (FPGA/ASIC)

Location: Austin, Boulder, Chicago, or New York in the United States; or London, United Kingdom

Salary: $175,000–$250,000 per year, plus discretionary performance-based bonuses and benefits

Company

hirify.global applies scientific computing and algorithmic trading technology to financial markets.

What you will do

• Create testbenches and tests for FPGA and ASIC hardware platforms using flexible open-source and proprietary environments.
• Write detailed verification plans and manage test suites.
• Collect and analyze code and functional coverage.
• Root-cause RTL bugs and debug existing designs.
• Collaborate directly with hardware designers during project bring-up.
• Develop and improve internal and open-source verification tools and continuous integration infrastructure.

Requirements

• 2+ years of professional experience in RTL functional verification for FPGA or ASIC.
• Experience with SystemVerilog and industry-standard verification frameworks such as UVM.
• Experience with Python and comfort working in a Linux environment.
• Strong debugging and analytical skills.
• A bachelor’s degree in computer science, electrical engineering, or a related field.
• Experience with code and functional coverage collection and analysis.

Nice to have

• Familiarity with Verilator and/or Cocotb.
• C++ experience.
• Financial experience is not required.

Culture & Benefits

• Work in a high-performance hardware and machine learning accelerator environment supporting algorithmic trading.
• Collaborate in an open and transparent engineering culture that values ideas from both experienced and new team members.
• Join a diverse global organization with colleagues across multiple offices.
• Receive a competitive benefits package and eligibility for discretionary performance-based bonuses.