Sr Principal Engineer Design, CPU Microarchitecture & RTL Design (RISC-V)

Location: Santa Clara, United States

Salary: $188,000–$325,000 per year

Company

hirify.global is a full-service semiconductor foundry providing chip design, development, and fabrication services with a global manufacturing footprint.

What you will do

• Lead microarchitecture definition and RTL design for critical blocks in advanced RISC-V CPU cores.
• Develop high-performance vector processing architectures, custom CPU extensions, and AI-enabled matrix acceleration engines.
• Conduct architectural exploration and microarchitectural research, translating concepts into detailed specifications.
• Refine RTL implementations to meet performance, power, area, timing, and scalability objectives.
• Support verification planning, debugging, waveform analysis, and coverage analysis.
• Collaborate with architectural modeling, physical design, DFT, implementation, and verification teams.

Requirements

• Master’s degree in electrical engineering, computer engineering, computer science, or a related technical discipline; PhD candidates may also be considered.
• 12+ years of industry experience with a master’s degree, or 6+ years with a PhD, in CPU, GPU, or advanced processor design.
• Hands-on experience with high-performance processors, vector processors, accelerators, or GPU architecture.
• Deep knowledge of CPU microarchitecture, including execution pipelines, instruction scheduling, register renaming, out-of-order execution, memory ordering, vector datapaths, and cache or memory subsystems.
• Strong RTL design expertise using Verilog, SystemVerilog, and/or VHDL, plus experience with simulation, debugging, and design verification methodologies.
• Understanding of logic design principles and timing, power, and area tradeoffs, along with strong analytical, communication, and teamwork skills.

Nice to have

• Experience designing RISC-V, ARM, or MIPS processor architectures.
• Experience with hardware multithreading, virtualization, SIMD, vector, or matrix-enabled CPU designs.
• Knowledge of AI acceleration techniques and processor extensions for machine learning workloads.
• Experience with Python, Perl, or Tcl for design automation and analysis.
• Understanding of SoC-level CPU integration and safety- or security-focused microarchitecture features.

Culture & Benefits

• Full-time employment with hirify.global.
• Work includes collaboration across CPU, AI accelerator, verification, physical design, DFT, and implementation disciplines.
• Employment is subject to applicable pre-employment conditions and laws.
• Reasonable accommodations are available during the employment process.