Senior RTL Design Engineer - CPU Frontend (RISC-V)

Location: Santa Clara, California, United States. The role requires satisfactory proof of the right to work in the United States of America and authorization to access export-controlled technology or the ability to obtain the required export licenses or approvals.

Base pay range: $158,760.00–$194,040.00 per year, with possible variable or incentive compensation and/or equity.

Company

hirify.global develops high-performance RISC-V compute platforms and processor technologies for AI, machine learning, automotive, data center, mobile, and consumer applications.

What you will do

• Architect, design, and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
• Integrate design content into the Chisel/FIRRTL framework and improve automatic generation of documentation, verification testbenches, tests, and packaged software.
• Perform initial sandbox verification and collaborate with the design verification team on thorough verification test plans and execution.
• Work with the physical implementation team to optimize designs for frequency, area, and power targets.
• Collaborate with the performance modeling team on performance exploration and optimization.
• Develop and specify microarchitecture while documenting designs and sharing knowledge through collaborative engineering.

Requirements

• BS/MS degree in computer science, computer engineering, electrical engineering, or a related field, or equivalent experience.
• 3+ years of design experience.
• Academic or professional CPU RTL design experience in one or more of instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, or TLBs.
• Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Strong software engineering skills in object-oriented, aspect-oriented, and particularly functional programming.
• Experience with templated metaprogramming, compiler infrastructures for domain-specific languages, and data modeling for intermediate representations used to optimize or transform compiler passes.
• Test-driven development skills, particularly the ability to write adaptive unit tests.
• Attention to detail and focus on high-quality design.
• Ability to collaborate effectively and share a belief that engineering is teamwork.

Nice to have

• Experience with Scala/Chisel, Bluespec, or another language/DSL for expressing configurable hardware through software.
• Knowledge of RISC-V architecture.
• Expertise in CPU processor design involving instruction fetch, instruction decode, register renaming and instruction scheduling, vector units, or load-store units.
• Knowledge of verification principles, testbenches, UVM, and coverage.
• Experience with Git/GitHub, Jira, and Confluence.

Culture & Benefits

• Collaborative engineering culture focused on knowledge sharing, inclusion, and teamwork.
• Comprehensive benefits package that may include healthcare, retirement plans, and paid time off.
• Potential eligibility for variable or incentive compensation and/or equity.
• Employment is subject to successful background and reference checks.
• hirify.global is an equal opportunity employer and an E-Verify employer.