Senior RTL Design Engineer - CPU Frontend (RISC-V)

Location: Santa Clara, California, United States

Salary: $158,760–$194,040 per year, plus potential variable or incentive compensation and equity.

Company

hirify.global develops RISC-V compute platforms and processor solutions for high-performance and data-intensive applications across AI, machine learning, automotive, data center, mobile, and consumer markets.

What you will do

• Architect, design, and implement features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
• Integrate design content into the Chisel/FIRRTL framework and improve automated generation of documentation, verification testbenches, tests, and packaged software.
• Perform initial sandbox verification and collaborate with design verification engineers on detailed verification plans and execution.
• Work with physical implementation engineers to optimize designs for frequency, area, and power targets.
• Collaborate with performance modeling engineers on performance exploration and optimization.
• Develop and document microarchitecture specifications while sharing knowledge through collaborative design.

Requirements

• BS/MS degree in computer science, computer engineering, electrical engineering, or a related field, or equivalent experience.
• At least 3 years of design experience.
• Academic or professional CPU RTL design experience in instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, or TLBs.
• Proficiency in Verilog, SystemVerilog, or VHDL RTL design.
• Strong software engineering background covering object-oriented and functional programming, templated metaprogramming, compiler infrastructure, data modeling, and test-driven development.
• Successful background and reference checks, proof of the right to work in the United States, and authorization to access export-controlled technology or obtain the necessary export approvals are required.

Nice to have

• Experience with Scala/Chisel, Bluespec, or another language or DSL for configurable hardware.
• Knowledge of RISC-V architecture and CPU processor design, including instruction fetch, instruction decode, register renaming, instruction scheduling, vector units, or load-store units.
• Knowledge of verification principles, testbenches, UVM, and coverage.
• Experience with Git/GitHub, Jira, or Confluence.

Culture & Benefits

• Collaborative engineering culture focused on teamwork, knowledge sharing, and high-quality design.
• Comprehensive benefits package that may include healthcare and retirement plans.
• Paid time off and additional employee benefits.
• Equal opportunity and inclusive workplace commitment.