Staff RTL Design Engineer - CPU LS/PF/MMU (RISC-V)

Location: Santa Clara, California, United States. Proof of the right to work in the United States is required, along with authorization to access export-controlled technology or the ability to obtain the necessary export approvals.

Base pay range: $178,848–$218,592 per year, plus potential variable or incentive compensation and equity.

Company

hirify.global develops high-performance computing platforms and CPU cores based on the open-standard RISC-V architecture for markets including artificial intelligence, machine learning, automotive, data center, mobile, and consumer devices.

What you will do

• Architect, design, and implement features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
• Integrate design content into the Chisel/FIRRTL framework and improve automated generation of documentation, verification testbenches, tests, and packaged software.
• Perform initial sandbox verification and collaborate with the design verification team on verification plans and execution.
• Work with physical implementation engineers to optimize designs for frequency, area, and power targets.
• Collaborate with performance modeling engineers on performance exploration and optimization.
• Develop microarchitecture specifications, document design decisions, and share technical knowledge across the engineering team.

Requirements

• BS or MS degree in computer science, computer engineering, electrical engineering, or a related field, or equivalent experience.
• 3+ years of design experience, including academic or professional CPU RTL design.
• Proficiency in Verilog, SystemVerilog, or VHDL for hardware RTL design.
• Strong software engineering background, including object-oriented, aspect-oriented, and functional programming, plus test-driven development and adaptive unit testing.
• Knowledge of verification principles, SVA, and coverage, with strong attention to detail and design quality.
• Must have the right to work in the United States and satisfy applicable export-control access requirements.

Nice to have

• Experience with Scala/Chisel, Bluespec, or another language or DSL for generating configurable hardware.
• Knowledge of the RISC-V instruction set architecture.
• Expertise in out-of-order processor microarchitecture, design, and verification, especially load-store units, coherent caches, cache prefetching, or virtual-memory MMU/TLBs.
• Familiarity with Git/GitHub, Jira, and Confluence.

Culture & Benefits

• Collaborative engineering culture focused on knowledge sharing and teamwork.
• Healthcare and retirement plans may be included in the benefits package.
• Paid time off and other competitive employee benefits.
• Employment is contingent on successful background and reference checks.