Staff RTL Design Engineer - CPU LS/PF/MMU (RISC-V)

Location: Santa Clara, California, United States. Requires satisfactory proof of the right to work in the United States and authorization to access export-controlled technology, or the ability to obtain the necessary export licenses or approvals.

Base pay range: $178,848.00–$218,592.00 annually. The role may also include variable or incentive compensation, equity, healthcare, retirement plans, and paid time off.

Company

hirify.global develops high-performance compute platforms and processor IP based on the open-standard RISC-V architecture for markets including artificial intelligence, machine learning, automotive, data center, mobile, and consumer hardware.

What you will do

• Architect, design, and implement features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
• Integrate design content into the Chisel/FIRRTL framework and improve automatic generation of documentation, verification testbenches, tests, and packaged software.
• Perform initial sandbox verification and collaborate with the design verification team on thorough verification test plans and execution.
• Work with physical implementation engineers to optimize designs for frequency, area, and power goals.
• Collaborate with performance modeling engineers on performance exploration and optimization.
• Develop microarchitecture specifications, document design knowledge, and participate in collaborative engineering.

Requirements

• BS or MS degree in computer science, computer engineering, electrical engineering, or a related field, or equivalent experience.
• 3+ years of design experience.
• Academic or professional experience with CPU RTL design.
• Proficiency in hardware RTL design using Verilog, SystemVerilog, or VHDL.
• Strong software engineering background, including object-oriented, aspect-oriented, and particularly functional programming.
• Test-driven development experience, especially the ability to write adaptive unit tests.
• Attention to detail, focus on high-quality design, and knowledge of verification principles, SVA, and coverage.
• Ability to collaborate effectively and share the belief that engineering is teamwork.

Nice to have

• Experience with Scala/Chisel, Bluespec, or another language or DSL for generating configurable hardware through software.
• Knowledge of the RISC-V instruction set architecture.
• Expertise in out-of-order processor microarchitecture, design, and verification in one or more areas: load-store units, coherent caches, cache prefetching, or virtual memory MMU/TLBs.
• Familiarity with Git/GitHub, Jira, and Confluence.

Culture & Benefits

• Collaborative engineering environment focused on sharing knowledge and developing high-quality processor solutions.
• Comprehensive benefits may include healthcare, retirement plans, and paid time off.
• Potential eligibility for variable or incentive compensation and equity.
• Equal opportunity employer committed to diversity and an inclusive environment.

Hiring process

• Employment is contingent on successful background and reference checks.
• New hires must complete Form I-9 employment eligibility verification.
• Authorization to access export-controlled technology must be verified or obtained through required export licenses or approvals.