Senior Staff RTL Design Engineer - CPU Frontend (RISC-V)

Location: Santa Clara, California, United States. Right to work in the United States of America is required. Access to export-controlled technology is subject to applicable authorization or export licensing.

Base pay range: $205,740–$251,460 per year, with possible variable or incentive compensation and equity.

Company

hirify.global develops high-performance compute platforms and CPU cores based on the open-source RISC-V architecture for applications including artificial intelligence, automotive, data center, mobile, and consumer technology.

What you will do

• Architect, design, and implement features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
• Integrate design content into the Chisel/FIRRTL framework and improve automatic generation of documentation, verification testbenches, tests, and packaged software.
• Perform initial sandbox verification and collaborate with design verification engineers on thorough verification plans and execution.
• Work with physical implementation engineers to optimize designs for frequency, area, and power goals.
• Collaborate with performance modeling engineers on performance exploration and optimization.
• Develop microarchitecture specifications and share technical knowledge through documentation and collaborative design.

Requirements

• BS/MS degree in computer science, computer engineering, electrical engineering, or a related field, or equivalent experience.
• 7+ years of design experience.
• CPU RTL design experience in instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, or TLBs.
• Proficiency in Verilog, SystemVerilog, or VHDL hardware design.
• Strong software engineering background, including functional programming, templated metaprogramming, compiler infrastructure, intermediate representations, and test-driven development.
• Attention to detail and ability to collaborate effectively and share knowledge.

Nice to have

• Experience with Scala/Chisel, Bluespec, or another software-based configurable hardware language or DSL.
• Knowledge of RISC-V architecture and CPU processor design, including register renaming, instruction scheduling, vector units, or load-store units.
• Knowledge of verification principles, testbenches, UVM, and coverage.
• Experience with Git/GitHub, Jira, or Confluence.

Culture & Benefits

• Collaborative engineering culture focused on high-quality CPU and hardware innovation.
• Healthcare and retirement plans may be included in the benefits package.
• Paid time off and other comprehensive benefits are available.
• Employment is contingent on successful background and reference checks and completion of employment eligibility verification.