18 часов назад
Interconnect Design Engineer (RISC-V/Chisel)
139 752 - 170 808$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Interconnect Design Engineer (RISC-V/Chisel): Designing configurable TileLink interconnects, cache controllers, protocol bridges, and uncore logic as Chisel RTL generators with an accent on hardware configurability, coherence, and high-performance SoC infrastructure. Focus on architecting protocol bridges, integrating designs into the Chisel/FIRRTL framework, and creating verification plans for configurable hardware IP.
Location: Santa Clara, California, United States. Right to work in the United States is required.
Base salary: $139,752–$170,808 per year, plus potential variable or incentive compensation and equity.
Company
develops customizable RISC-V CPU, interconnect, and infrastructure IP for advanced SoC applications.
What you will do
- Design and implement TileLink interconnects, cache controllers, protocol bridges, and other uncore infrastructure as Chisel RTL generators.
- Develop self-configuring RTL generators and add extensive configurability to hardware designs.
- Improve performance, efficiency, and coherence across multi-core and multi-system designs.
- Integrate hardware IP into the Chisel/FIRRTL framework and improve automated configuration, documentation, verification, testing, and software packaging.
- Perform initial verification and collaborate with the design verification team on thorough test plans.
- Document designs and share technical knowledge through collaborative engineering.
Requirements
- Junior-level hardware engineering experience with a BS/MS in EE, CE, CS, or a related technical discipline, or equivalent experience.
- Knowledge of cache and cache-coherency architectures and experience with NoC or other interconnect fabrics.
- Familiarity with AXI, AHB, APB, or CHI bus protocols and the ability to connect disparate bus fabrics.
- Strong software engineering background in functional programming, metaprogramming, compiler infrastructure, data modeling, and test-driven development.
- Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
- Attention to detail, high-quality design practices, and effective collaboration skills.
Nice to have
- Experience with Scala/Chisel, Bluespec, or another software-based language or DSL for configurable hardware.
- Knowledge of RISC-V architecture.
- Experience with Git/GitHub, Jira, or Confluence.
Culture & Benefits
- Collaborative engineering culture focused on knowledge sharing and team-based design.
- Healthcare and retirement plans may be included in the benefits package.
- Paid time off and other competitive benefits are available.
- Employment is subject to background and reference checks, employment eligibility verification, and export-control authorization requirements.
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