3 часа назад
Senior Engineer, SoC Architecture – Memory Subsystem and Interconnect (ARM/DRAM)
158 800 - 218 100$
Мэтч & Сопровод
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Описание вакансии
Текст:
TL;DR
Senior Engineer, SoC Architecture – Memory Subsystem and Interconnect (ARM/DRAM): Architecting next-generation SoC fabric, system cache, and DRAM controller subsystems with an accent on power, performance, memory bandwidth, latency, and QoS tradeoffs. Focus on performance modeling and simulation, developing microarchitectural proposals, and collaborating with hardware, software, silicon bring-up, and product teams.
Location: Onsite at 665 Clyde Avenue, Mountain View, California, USA
Base pay range: $158,800–$218,100 USD annually, with annual bonus eligibility and benefits.
Company
develops SoC architecture, bus and memory subsystems, multimedia subsystems, and key IP blocks for future Galaxy devices in collaboration with Samsung teams and strategic SoC partners.
What you will do
- Architect fabric, system cache, and DRAM controller subsystems for next-generation SoCs.
- Develop architectural and microarchitectural features to improve power and performance across targeted workloads.
- Evaluate architecture proposals through high-level performance modeling, simulation, benchmarking, and analysis.
- Define and communicate architecture and microarchitecture specifications to hardware, software, architecture, and technology leadership audiences.
- Collaborate with silicon bring-up and product teams to verify and debug delivered performance.
- Coordinate cross-functional implementation across the SoC, drivers, operating systems, and system teams.
Requirements
- Bachelor’s, master’s, or doctoral degree in Computer Science, Computer Engineering, or equivalent education and experience.
- 3+ years of experience in SoC or ASIC design and architecture.
- Direct experience with fabric, system cache, DRAM controller architecture, or microarchitecture.
- Knowledge of memory controller architecture, memory scheduling, prioritization, and QoS.
- Detailed knowledge of ARM bus infrastructure, including ACE, AXI, and AHB.
- Knowledge of one or more JEDEC standards such as LPDDR, DDR, or HBM, plus an understanding of memory bandwidth, latency, performance, power, and SoC area tradeoffs.
Nice to have
- Experience with BookSim Simulator.
- Experience with Platform Architect.
Culture & Benefits
- Inclusive and diverse work environment with equal employment opportunities.
- Comprehensive compensation package with annual bonus eligibility.
- Generous employee benefits.
- Office-based work setting with reasonable accommodation available during the employment selection process.
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