RTL Engineer, Networking ASIC

Location: Saratoga, CA, United States

Company

hirify.global is a Silicon Valley hardware startup developing silicon, packaging, software, and systems solutions that accelerate AI data centers.

What you will do

• Define, specify, architect, implement, and productize networking ASICs.
• Design packet buffering, queuing, scheduling, arbitration, and on-chip memory subsystems for high-speed networking chips.
• Optimize latency, pipelining architectures, performance, and quality-of-service mechanisms.
• Support Ethernet, IP, UCIe, and other high-speed networking protocols.
• Implement and test ASIC designs against industry standards and performance benchmarks.
• Debug complex packet-queuing issues in collaboration with system architects, hardware engineers, firmware developers, and verification engineers.

Requirements

• ME or BE degree with 8–15 years of relevant experience.
• Hands-on experience with SystemVerilog and Verilog is mandatory.
• Strong understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.
• Expertise in scheduling and QoS mechanism design and optimization.
• Experience with Ethernet and IP protocols.
• Strong analytical, troubleshooting, debugging, communication, and collaboration skills.

Culture & Benefits

• Work with an experienced engineering team developing AI infrastructure technology.
• Contribute directly to next-generation AI data center performance.
• Join a startup backed by more than $200 million in funding and supported by leading hyperscalers and supply-chain partners.
• Base salary is determined according to skills, experience, qualifications, work location, market trends, and comparable employee compensation.