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12 часов назад

Senior Principal ASIC Design Engineer (AI Infrastructure)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Germany
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Principal ASIC Design Engineer (AI Infrastructure): Defining and delivering ASIC architectures for next-generation Ethernet and scale-up connectivity products with an accent on UALink, UCIe, PCIe Gen 6/7, Ethernet, and high-performance networking. Focus on designing RTL, packet-processing pipelines, RDMA and DMA acceleration, congestion management, and taking complex silicon from architecture through tapeout and post-silicon bring-up.

Location: Germany (onsite)

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating Ethernet, CXL, NVLink, PCIe, and UALink technologies.

What you will do

  • Define ASIC architecture and microarchitecture for Ethernet and scale-up connectivity products.
  • Lead RTL design for Ethernet controllers, MACs, NIC datapaths, packet-processing engines, and AI networking subsystems.
  • Design data movement, scheduling, buffering, queue management, flow control, congestion management, QoS, DMA, and memory interfaces.
  • Develop hardware acceleration for RDMA, virtualization, protocol offloads, zero-copy data movement, and transport reliability.
  • Drive ASIC execution from architecture and RTL through integration, verification, synthesis, timing closure, tapeout, and post-silicon validation.
  • Set technical direction across teams and collaborate with firmware, software, digital, networking, and systems groups.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 12+ years of ASIC/SoC design experience delivering complex networking or connectivity silicon from architecture through production.
  • Deep expertise in RTL design and microarchitecture for high-performance networking ASICs.
  • Experience with Ethernet controllers, MACs, NIC architectures, packet processing, RDMA, DMA, scheduling, buffering, queue management, flow control, and congestion management.
  • Strong understanding of Ethernet, PCIe, and AI scale-up interconnects, plus hands-on experience across the complete ASIC development flow.
  • Demonstrated technical leadership across multiple teams and product programs.

Nice to have

  • Master’s or PhD in Electrical Engineering, Computer Engineering, or a related technical discipline.
  • Experience with UALink, UCIe, PCIe Gen 6/7, advanced Ethernet architectures, SmartNICs, DPUs, NICs, or switch datapaths.
  • Experience delivering Ethernet-based scale-up networking solutions for AI and HPC systems.
  • Experience leading multiple advanced-node ASIC tapeouts.
  • Strong communication, collaboration, and mentorship skills.

Culture & Benefits

  • Work in a technically diverse environment focused on creativity and innovation.
  • Collaborate across digital, networking, systems, firmware, and software domains.
  • Inclusive workplace encouraging applications from people with diverse backgrounds and experiences.

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