Sr. ASIC Design Engineer (Networking)

Location: Onsite at an HPE office in the United States; the stated salary range applies to California.

Salary: USD 153,500–310,500 annual base salary in California, with possible variable incentives.

Company

hirify.global develops edge-to-cloud technologies, including networking routers, switches, and high-density networking chips.

What you will do

• Translate functional specifications into detailed micro-architecture specifications that meet power and area requirements.
• Implement ASIC designs using Verilog or SystemVerilog.
• Write functional coverage and SVA to identify corner-case bugs during verification.
• Collaborate with Physical Design on floorplanning, timing closure, and RTL timing fixes to meet frequency targets.
• Work with Verification to fully validate design blocks.
• Mentor new college-graduate engineers and interns.

Requirements

• Bachelor’s degree in Electrical Engineering and 5+ years of relevant experience; a Master’s degree is strongly desired.
• Strong analytical and problem-solving skills.
• Strong Verilog or SystemVerilog coding skills.
• Knowledge of synthesis, lint, and other EDA tools.
• Knowledge of computer architecture and networking protocols is beneficial.
• Strong written and verbal communication skills.

Nice to have

• Knowledge of Perl or Python.
• Experience with AI agentic tools.

Culture & Benefits

• Comprehensive health, financial, and emotional wellbeing benefits for employees and their families.
• Personal and professional development programs supporting career growth and internal mobility.
• Inclusive workplace that values varied backgrounds and individual uniqueness.
• Flexible support for managing work and personal needs.