Director of Design Verification (Chiplets)

Location: Bay Area, United States; on-site

Company

hirify.global is a chiplet startup developing high-performance, manufacturable chiplet-based system technologies.

What you will do

• Define and own verification strategy and methodology across multiple PHY and controller product lines, including D2D, UCIe, and Ethernet interfaces.
• Build, mentor, and manage the verification team while establishing UVM-based, coverage-driven, and formal verification best practices.
• Drive verification planning and execution for link layer, PCS, PMA, FEC, auto-negotiation, and link training subsystems.
• Establish AMS verification flows using RNM, SVAMS co-simulation, and analog behavioral model integration into digital environments.
• Partner with design, architecture, DFT, and physical design teams on micro-architecture reviews, test-plan completeness, and coverage closure.
• Own milestones across concurrent tapeout programs, manage risks, report to executive leadership, and improve regression, CI/CD, coverage analytics, and productivity tooling.
• Ensure compliance with IEEE 802.3, UCIe, and emerging D2D specifications; manage third-party VIPs, AMS verification IP, vendor relationships, and issue tracking.
• Oversee DPI-based firmware co-simulation, system-level PHY bring-up and validation, and GLS environments for functional, timing, and power-aware simulations.

Requirements

• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• 15+ years of design verification experience with high-speed serial interfaces, PHYs, and controller IPs, including at least 5 years in people management or leadership.
• Deep expertise in SystemVerilog/UVM, constrained-random verification, assertion-based verification, and formal verification.
• Experience with AMS verification, including RNM, Verilog-AMS, SVAMS co-simulation, and mixed-signal behavioral modeling.
• Strong knowledge of link layer protocols, PCS architectures, RS-FEC, KP4, KR4, Ethernet 802.3 clauses for 100G/200G/400G/800G, and UCIe.
• Experience driving verification innovation through automation, AI/ML-assisted verification, and scalable productivity methodologies.
• Hands-on experience verifying PLLs, CDRs, SerDes analog front-ends, DLLs, and integrating analog models into digital verification environments.
• Experience building and scaling verification teams in startup or high-growth environments with multiple concurrent tapeouts.

Nice to have

• Experience with DRAM controllers or PHYs, HBM memory interfaces, and/or optical interconnect verification.

Culture & Benefits

• Fast-paced startup environment focused on chiplet-based systems.
• Cross-functional collaboration with engineering experts working from first principles.
• Fun work environment with excellent benefits.