6 часов назад
Director of Design Verification (Chiplet/AMS)
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Director of Design Verification (Chiplet/AMS): Leading verification strategy and scaling a verification team across PHY and controller products for chiplet-based systems with an accent on UVM, formal verification, and analog/mixed-signal flows. Focus on driving coverage closure, managing concurrent tapeout programs, integrating AMS models and VIPs, and ensuring signoff readiness for high-speed interconnects.
Location: Bay Area, United States; on-site
Company
is a chiplet startup developing technologies for high-performance, manufacturable chiplet-based systems.
What you will do
- Define and own verification strategy and methodology across PHY and controller product lines, including D2D, UCIe, and Ethernet interfaces.
- Build, mentor, and manage a verification organization using UVM, coverage-driven verification, formal methods, and scalable automation.
- Drive verification planning and execution for link layer, PCS, PMA, FEC, auto-negotiation, and link training subsystems.
- Establish analog/mixed-signal verification flows with RNM, Verilog-AMS, SVAMS co-simulation, and behavioral model integration.
- Partner with architecture, design, DFT, and physical design teams to complete test plans, coverage closure, milestones, and tapeout deliverables.
- Oversee VIP and AMS verification IP integration, firmware co-simulation, GLS, CI/CD infrastructure, and system-level PHY validation.
Requirements
- Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
- 15+ years of design verification experience with high-speed serial interfaces, PHYs, and controller IPs, including at least 5 years in people management or leadership.
- Expertise in SystemVerilog/UVM, constrained-random verification, assertion-based verification, and formal verification.
- Experience with RNM, Verilog-AMS, SVAMS co-simulation, mixed-signal behavioral modeling, and verification of PLLs, CDRs, SerDes analog front-ends, and DLLs.
- Strong knowledge of PCS architectures, RS-FEC/KP4/KR4, Ethernet 802.3 for 100G–800G, UCIe, and die-to-die interconnect standards.
- Experience building and scaling verification teams in startup or high-growth environments with concurrent tapeouts.
Nice to have
- Experience with DRAM Controllers/PHYs, HBM memory interfaces, or optical interconnect verification.
- Experience with AI/ML-assisted verification and productivity improvements.
Culture & Benefits
- Fast-paced startup environment focused on high-volume, high-performance, manufacturable products.
- Cross-functional work with design, architecture, DFT, and physical design experts.
- Excellent benefits and a collaborative work environment.
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