Distinguished ASIC Design Engineer (AI Connectivity)

Location: Germany (onsite)

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and a software suite integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.

What you will do

• Define ASIC architecture for Ethernet and Scale-Up connectivity products using UALink, UCIe, PCIe Gen 6/7, and Ethernet.
• Lead microarchitecture and RTL design for Ethernet controllers, MACs, NIC datapaths, packet-processing engines, and AI interconnect fabrics.
• Design packet parsing, DMA, queue management, scheduling, buffering, flow control, congestion management, and protocol acceleration.
• Develop hardware support for RDMA, zero-copy data movement, virtualization, multi-tenant isolation, traffic management, and QoS.
• Define hardware/software interfaces with firmware and software teams for initialization, telemetry, monitoring, and diagnostics.
• Drive execution from architecture through integration, verification, tapeout, and post-silicon bring-up while meeting performance, timing, power, area, manufacturability, and reliability targets.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 15+ years of ASIC/SoC design experience delivering complex high-speed networking or connectivity silicon from architecture through production.
• Deep expertise in RTL design and microarchitecture for networking and connectivity ASICs.
• Extensive experience with Ethernet controllers, MACs, NIC architectures, packet-processing engines, or network interface subsystems.
• Strong understanding of RDMA, RoCE or similar low-latency networking technologies, as well as Ethernet, PCIe, and AI scale-up fabrics.
• Experience across the complete ASIC development flow, including synthesis, timing closure, physical implementation, tapeout, and post-silicon validation, with demonstrated technical leadership across teams and programs.

Nice to have

• Master’s or PhD in Electrical Engineering, Computer Engineering, or a related technical discipline.
• Direct experience with UALink, UCIe, PCIe Gen 6/7, or advanced Ethernet architectures and protocols.
• Experience with Ethernet MACs, SmartNICs, DPUs, NICs, switch datapaths, or packet-processing engines.
• Experience developing Ethernet-based scale-up networking for AI and HPC systems.
• Experience leading multiple advanced-node ASIC tapeouts, along with strong communication, collaboration, and mentorship skills.

Culture & Benefits

• Work with cross-functional teams spanning digital, networking, system, firmware, and software domains.
• Contribute to an environment that values creativity, innovation, and diverse ideas, backgrounds, and experiences.
• Applications are encouraged from candidates with relevant experience across diverse backgrounds and identities.