Principal Engineer - Design (Verilog/SystemVerilog)

Location: Hauppauge, New York, United States; travel required 0–25%

Annual base salary: $75,000–$232,000, plus restricted stock units and quarterly bonuses

Company

Global semiconductor technology organization developing connectivity products and solutions for networking and communications.

What you will do

• Contribute to the Networking and Communications Group Design Team.
• Develop advanced connectivity devices, including Ethernet switches and bridges, USB hubs and power delivery, PCIe bridges, serial interfaces, and other connectivity interfaces.
• Execute digital design projects using Verilog and SystemVerilog.
• Work with ASIC design and verification flows.
• Apply simulation tools and support Xilinx FPGA emulation and debugging.
• Collaborate with engineers on problem solving, debugging, communication, and documentation.

Requirements

• Bachelor’s degree in Electrical Engineering or an equivalent engineering discipline.
• 10+ years of relevant industry experience.
• Experience with Ethernet, USB, and/or PCIe.
• Proficiency in Verilog and SystemVerilog.
• Experience with ASIC design and/or verification flows.
• Strong analytical, communication, documentation, problem-solving, debugging, and organizational skills.

Nice to have

• Knowledge of USB 3.0, USB 2.0, USB Power Delivery, PCIe, Ethernet 10/100/1G BASE-T, and 1G–25G SerDes.
• Experience with SPI, I2C, UART, and similar peripheral interfaces.
• Experience with simulation tools and Xilinx FPGA emulation and debugging.

Culture & Benefits

• Health benefits begin on the first day.
• Retirement savings plans and an employee stock purchase program with a two-year look-back feature.
• Competitive total compensation including base pay, restricted stock units, and quarterly bonuses.
• Collaborative environment focused on employee development, innovation, and values-based decision making.
• Physical requirements include approximately 80% sitting, 10% standing, and 10% walking.