DFT Engineer

Location: Saratoga, CA, United States

Company

hirify.global is a Silicon Valley hardware startup developing silicon, packaging, software, and systems that accelerate AI data centers and improve performance, power efficiency, cost, and reliability.

What you will do

• Define the DFT architecture for multi-chip system-on-chip designs.
• Develop scan, BIST, memory repair, boundary scan, and other test design functions.
• Define and implement on-chip clock control, with exposure to LBIST and streaming DFT techniques.
• Supervise ATPG generation and achieve high coverage for scan and at-speed scan testing.
• Work with synthesis design constraints, including SDC, and DFT and simulation CAD tools.
• Perform RTL- and gate-level simulation and collaborate with logic and physical design teams.

Requirements

• Master’s or bachelor’s degree in electrical engineering.
• 15+ years of relevant experience, including multiple deep-submicron tape-outs at 7nm or below.
• Experience with synthesis, DFT, simulation, and Mentor or Synopsys test tools.
• Strong scripting skills in Unix, Perl, Python, or TCL.
• Knowledge of Verilog and SystemVerilog, device physics, and low-power, high-performance design principles.
• Experience with serializers/deserializers and the ability to work productively under aggressive schedules.

Nice to have

• Experience with EMIB architectures and bridge technologies.
• Exposure to advanced DFT techniques such as LBIST and streaming.

Culture & Benefits

• Work with an experienced engineering team spanning silicon, packaging, optics, software, and systems.
• Contribute to next-generation AI infrastructure and data-center performance.
• Join a startup backed by more than $200 million in funding and supported by leading hyperscalers.
• Base salary is determined according to skills, experience, qualifications, work location, market trends, and comparable employee compensation.