9 часов назад
DFT - Staff DFT Engineer
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
DFT - Staff DFT Engineer (Chiplet DFT): Defining and implementing scan, memory BIST, IEEE 1149.x/1687/1500/1838 structures, and ATPG patterns for chiplet-based systems with an accent on test coverage, manufacturability, and high-speed interface testing. Focus on validating DFT structures at RTL and gate level, automating test flows, bringing up patterns in the lab and on ATE, and narrowing coverage gaps.
Location: Bay Area, United States; on-site
Company
is an early-stage chiplet startup developing technologies for high-volume, high-performance chiplet-based systems.
What you will do
- Define DFT strategy, methodologies, and implementation plans for chip-level designs and standalone IP blocks such as PHYs and chiplets.
- Implement DFT features in RTL for digital and analog blocks.
- Generate and validate 1687 PLD, 1149.x, MBIST, ATPG, SA, and TDF patterns at RTL and gate level.
- Collaborate with AMS and circuit architecture teams on high-speed interface coverage, structural tests, PRBS-based PHY loopback, and clock-network measurement.
- Automate DFT flows with scripting and support device bring-up, ATE pattern handoff, qualification, and RMA analysis.
- Document test coverage and mitigation strategies for coverage gaps.
Requirements
- Proficiency in modern DFT/DFx techniques and tools, including scan insertion, ATPG, and MBIST.
- Working knowledge of IEEE 1149.x, 1687, 1500, and 1838 standards.
- Proficiency in Verilog simulation and debugging of DFT structures at RTL and gate level.
- Experience taping out at least four designs and bringing up at least two designs on ATE or in a lab.
- Proficiency in TCL and shell scripting, plus working knowledge of Perl, Python, or a similar language and industry-standard development tools.
- BS in Electrical Engineering or equivalent and 6–9 years of experience; collaborative cross-functional work is required.
Nice to have
- Deep expertise in modern test methods, DFx methodologies, and test time, PPA, and coverage tradeoffs.
- Experience analyzing holistic device test coverage, including non-structural tests.
- Experience delivering hard and soft IP and creating design-kit collateral.
- 3+ years of experience with the Siemens Tessent platform, including ATPG, MBIST, iJTAG, BS, and SSN flows.
- MS or PhD in Electrical Engineering or equivalent.
Culture & Benefits
- Fast-paced early-stage startup environment.
- Cross-functional collaboration with experienced chip and circuit specialists.
- Work focused on manufacturable, high-performance chiplet technologies.
- Fun work environment with excellent benefits.
- AI tools may assist with parts of the hiring process, while final decisions remain with human reviewers.
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