Lead/Principal DFT Engineer (AI Accelerator)

Location: Bristol, United Kingdom

Company

hirify.global is an AI hardware startup building chips and systems designed to generate outputs from frontier AI models at thousands of tokens per second.

What you will do

• Own and define DFT architecture for a large AI accelerator SoC, including scan, compression, MBIST, LBIST, and boundary scan.
• Set DFT strategy, methodology, implementation flow, and signoff criteria.
• Integrate DFT tools and flows into the broader EDA environment and define hierarchical DFT for multi-core designs and large memory systems.
• Define scan, compression, ATPG, memory test, repair, power-aware, and at-speed test strategies.
• Collaborate with RTL and physical design teams on DFT integration and timing closure.
• Work with test and product engineering teams on ATE pattern bring-up, debug, production testing, and yield ramp while mentoring DFT engineers.

Requirements

• Typically 10+ years of experience in DFT for complex ASIC or SoC designs.
• Ownership of DFT architecture for at least one large tapeout.
• Deep expertise in scan, compression, ATPG, and MBIST.
• Experience with industry DFT tools such as Synopsys or Tessent.
• Strong understanding of clocking, resets, power domains, and physical constraints.
• Experience with silicon bring-up, debug, and yield ramp, with the ability to balance architectural direction and hands-on implementation.

Culture & Benefits

• Meaningful equity participation.
• Private medical, dental, and vision coverage.
• Contributory pension.
• 25 days of holiday plus bank holidays.
• Life and critical illness insurance.
• Inclusive office environment focused on diverse perspectives and equal employment opportunity.

Hiring process

• Some roles may require additional eligibility checks because the work is subject to UK, US, and other international export control regulations.