13 ΡΠ°ΡΠΎΠ² Π½Π°Π·Π°Π΄
Principal DFT Engineer (AI Connectivity)
ΠΡΡΡ & Π‘ΠΎΠΏΡΠΎΠ²ΠΎΠ΄
ΠΠ»Ρ ΠΌΡΡΡΠ° Ρ ΡΡΠΎΠΉ Π²Π°ΠΊΠ°Π½ΡΠΈΠ΅ΠΉ Π½ΡΠΆΠ΅Π½ Plus
ΠΠΏΠΈΡΠ°Π½ΠΈΠ΅ Π²Π°ΠΊΠ°Π½ΡΠΈΠΈ
Π’Π΅ΠΊΡΡ:
TL;DR
Principal DFT Engineer (AI Connectivity): Defining and leading design-for-test architecture, implementation, verification, and silicon bring-up for complex SoCs and chiplet-based AI connectivity solutions with an accent on Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG. Focus on building scalable DFT methodologies and automation, driving sign-off readiness, and ensuring test coverage, manufacturability, and first-pass silicon success.
Location: Tel Aviv-Yafo, Tel Aviv District, Israel
Company
develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure.
What you will do
- Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies.
- Lead DFT planning, specification, implementation, integration, verification, and sign-off across block, full-chip, and chiplet levels.
- Drive end-to-end DFT activities from specification through silicon bring-up and production support.
- Develop scalable DFT methodologies, flows, and automation frameworks.
- Collaborate with RTL, Physical Design, STA, and Test Engineering teams to improve DFT readiness, quality, PPA, and turnaround time.
Requirements
- Bachelorβs degree in Electrical Engineering or a related technical field; a Masterβs degree is preferred.
- 12+ years of experience in DFT design, implementation, and verification for complex ASIC or SoC designs.
- Proven experience leading DFT activities across full-chip development cycles.
- Deep expertise in Scan, MBIST, LBIST, JTAG/iJTAG, ATPG, DFT verification, and coverage analysis.
- Experience with DFT and Physical Design flows, timing implications, integration challenges, and industry-standard tools such as Siemens Tessent or Synopsys TestMAX.
- Strong scripting skills in Tcl, Python, or Perl for automation and flow development.
Nice to have
- Experience with advanced process nodes of 7nm and below.
- Background in high-speed connectivity designs such as PCIe, Ethernet, or CXL.
- Experience with hierarchical DFT and large multi-die or chiplet-based systems.
- Knowledge of silicon bring-up, production test flows, yield optimization, STA, low-power design, and CDC as related to DFT integration.
- Strong leadership and communication skills with the ability to influence global cross-functional teams.
Culture & Benefits
- Join a newly established strategic R&D center in Israel.
- Work on semiconductor technologies supporting large-scale AI clusters.
- Contribute to an inclusive environment that welcomes diverse backgrounds and experiences.
ΠΡΠ΄ΡΡΠ΅ ΠΎΡΡΠΎΡΠΎΠΆΠ½Ρ: Π΅ΡΠ»ΠΈ ΡΠ°Π±ΠΎΡΠΎΠ΄Π°ΡΠ΅Π»Ρ ΠΏΡΠΎΡΠΈΡ Π²ΠΎΠΉΡΠΈ Π² ΠΈΡ ΡΠΈΡΡΠ΅ΠΌΡ, ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΡ iCloud/Google, ΠΏΡΠΈΡΠ»Π°ΡΡ ΠΊΠΎΠ΄/ΠΏΠ°ΡΠΎΠ»Ρ, Π·Π°ΠΏΡΡΡΠΈΡΡ ΠΊΠΎΠ΄/ΠΠ, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡΠ΅ ΡΡΠΎΠ³ΠΎ - ΡΡΠΎ ΠΌΠΎΡΠ΅Π½Π½ΠΈΠΊΠΈ. ΠΠ±ΡΠ·Π°ΡΠ΅Π»ΡΠ½ΠΎ ΠΆΠΌΠΈΡΠ΅ "ΠΠΎΠΆΠ°Π»ΠΎΠ²Π°ΡΡΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡΠΈΡΠ΅ Π² ΠΏΠΎΠ΄Π΄Π΅ΡΠΆΠΊΡ. ΠΠΎΠ΄ΡΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β
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