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13 часов Π½Π°Π·Π°Π΄

Principal DFT Engineer (AI Connectivity)

Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
senior
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
Israel
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

ОписаниС вакансии

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TL;DR
Principal DFT Engineer (AI Connectivity): Defining and leading design-for-test architecture, implementation, verification, and silicon bring-up for complex SoCs and chiplet-based AI connectivity solutions with an accent on Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG. Focus on building scalable DFT methodologies and automation, driving sign-off readiness, and ensuring test coverage, manufacturability, and first-pass silicon success.

Location: Tel Aviv-Yafo, Tel Aviv District, Israel

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure.

What you will do

  • Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies.
  • Lead DFT planning, specification, implementation, integration, verification, and sign-off across block, full-chip, and chiplet levels.
  • Drive end-to-end DFT activities from specification through silicon bring-up and production support.
  • Develop scalable DFT methodologies, flows, and automation frameworks.
  • Collaborate with RTL, Physical Design, STA, and Test Engineering teams to improve DFT readiness, quality, PPA, and turnaround time.

Requirements

  • Bachelor’s degree in Electrical Engineering or a related technical field; a Master’s degree is preferred.
  • 12+ years of experience in DFT design, implementation, and verification for complex ASIC or SoC designs.
  • Proven experience leading DFT activities across full-chip development cycles.
  • Deep expertise in Scan, MBIST, LBIST, JTAG/iJTAG, ATPG, DFT verification, and coverage analysis.
  • Experience with DFT and Physical Design flows, timing implications, integration challenges, and industry-standard tools such as Siemens Tessent or Synopsys TestMAX.
  • Strong scripting skills in Tcl, Python, or Perl for automation and flow development.

Nice to have

  • Experience with advanced process nodes of 7nm and below.
  • Background in high-speed connectivity designs such as PCIe, Ethernet, or CXL.
  • Experience with hierarchical DFT and large multi-die or chiplet-based systems.
  • Knowledge of silicon bring-up, production test flows, yield optimization, STA, low-power design, and CDC as related to DFT integration.
  • Strong leadership and communication skills with the ability to influence global cross-functional teams.

Culture & Benefits

  • Join a newly established strategic R&D center in Israel.
  • Work on semiconductor technologies supporting large-scale AI clusters.
  • Contribute to an inclusive environment that welcomes diverse backgrounds and experiences.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’