Назад
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10 часов назад

Sr. Design for Test (DFT) Engineer

123 000 - 150 000CAD
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Sr. Design for Test (DFT) Engineer (ASIC/AI acceleration): Building and validating high-performance ASIC test infrastructure for next-generation AI acceleration systems with an accent on DFT insertion, ATPG, physical-design integration, and post-silicon bring-up. Focus on implementing scan, boundary scan, and memory BIST, automating DFT flows, closing timing, and debugging ATE test programs across multiple tapeouts.

Location: Toronto, ON; flexible hybrid workplace model

Salary: $123,000–$150,000 CAD per year, plus equity grants and performance-based equity

Company

hirify.global develops photonics-based data center infrastructure and high-performance systems for AI and HPC workloads.

What you will do

  • Insert DFT into ASIC designs, including internal scan, boundary scan, and memory BIST.
  • Generate automatic and targeted test patterns and automate DFT and ATPG flows.
  • Collaborate with physical design and RTL design teams on ASIC implementation.
  • Lead post-silicon DFT bring-up and test program debugging.
  • Interface with ATE engineers on test program bring-up and debug.
  • Contribute hands-on expertise from detailed implementation through high-level planning.

Requirements

  • Bachelor’s degree in Electrical Engineering or a related field.
  • At least 13 years of industry experience as a DFT Engineer working on ASIC designs.
  • At least two completed tapeouts and two years of experience with standard DFT CAD tools and flows.
  • Hands-on experience with Python, TCL, or other scripting environments.
  • DFT, post-silicon, and ATPG experience across ASIC and semi-custom COT flows.
  • Strong collaboration skills and the ability to work effectively in a fast-paced environment.

Nice to have

  • Master’s degree in Electrical Engineering or a related field with 10+ years of DFT experience.
  • Multiple production-quality ASIC tapeouts and ATE test program development experience.
  • Experience with fault modeling and understanding of timing, physical-design, and power impacts of DFT structures.
  • Knowledge of basic SoC architecture, SystemVerilog, and chipware components.

Culture & Benefits

  • Flexible hybrid workplace model.
  • Comprehensive medical, dental, and vision coverage.
  • Retirement savings matching program.
  • Vacation, sick leave, public holidays, and paid family leave.
  • Life insurance, short- and long-term disability coverage, training and development, and commuter benefits.
  • Equity grants for full-time employees.

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