8 часов назад
Senior/Staff DFT (Design for Test) Engineers
321 000 - 220 000$
Мэтч & Сопровод
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Описание вакансии
Текст:
TL;DR
Senior/Staff DFT (Design for Test) Engineers (ASIC): Architecting and implementing test strategies for high-performance AI accelerator silicon with an accent on scan, JTAG, boundary scan, Memory BIST, ATPG, and silicon bring-up. Focus on maximizing fault coverage and manufacturing yield, minimizing PPA impact, and integrating DFT across digital, mixed-signal, optical, and software domains.
Location: On-site in Austin, Texas, US or Bristol, UK
Salary: Starting from $321,000 in Austin or £220,000 in Bristol, plus equity.
Company
develops the DX-1 decode accelerator, a rack-scale AI hardware platform combining digital logic, data movement, packaging, optics, and interconnect.
What you will do
- Architect and own DFT strategies for complex, high-throughput digital pipelines in advanced CMOS nodes.
- Implement and verify Scan, JTAG, Boundary Scan, Memory BIST, and related DFT features.
- Develop and optimize ATE-compatible ATPG patterns to improve fault coverage and manufacturing yield.
- Develop DFT-focused RTL and collaborate on formal and constrained-random verification.
- Minimize DFT impact on power, performance, and area while defining interfaces with mixed-signal and software teams.
- Lead design reviews, mentor engineers, and drive testability and silicon debug practices through the ASIC lifecycle.
Requirements
- 7+ years of hands-on DFT architecture, implementation, and verification for high-performance ASICs or SoCs, including ownership of at least one product with comprehensive DFT coverage.
- Experience with Scan/ATPG, Boundary Scan, Memory BIST/Repair, compression, EDT, JTAG, IEEE 1149.1, and IEEE 1687.
- Expertise in scan insertion, pattern simulation, fault modeling, diagnosis, and large pattern-set management.
- Proficiency with Python and Tcl scripting for DFT automation, pattern management, and silicon debug.
- Experience with tape-out at 22 nm or below, plus knowledge of semiconductor device physics, fault models, and yield enhancement.
- Eligibility is subject to U.S. export control regulations and recent citizenship or permanent residency status; applicants from certain restricted countries may not be eligible.
Nice to have
- Knowledge of high-speed SerDes or HBM/DDR DFT challenges.
- Familiarity with AI/ML workloads or systolic arrays and their DFT implications.
- Contributions to open-source DFT tools or verification frameworks.
Culture & Benefits
- Meaningful stock options and ownership in the company.
- Annual Living-Local Bonus for residing within 20 minutes of the office.
- Employer-contributed retirement plans.
- Competitive compensation based on experience, skills, and location.
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