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ASIC Diagnostic & Silicon Bring-Up Engineer (AI Infrastructure)

Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
ASIC Diagnostic & Silicon Bring-Up Engineer (AI Infrastructure): Building diagnostic infrastructure, automation frameworks, and debug tools for post-silicon validation of high-performance ASICs with an accent on SERDES, Ethernet, PCIe, UCIe, and packet processing pipelines. Focus on leading silicon bring-up, automating register access and test orchestration in Python, and correlating RTL, emulation, firmware, and silicon behavior.

Location: Saratoga, CA, United States

Company

hirify.global is a Silicon Valley-based hardware startup developing infrastructure solutions for AI data centers across silicon, packaging, software, and systems.

What you will do

  • Develop diagnostics for early silicon validation, post-silicon debug, and continuous validation.
  • Lead ASIC silicon bring-up on characterization and validation platforms.
  • Validate power, reset, clocking, register access, and initialization flows.
  • Build Python-based diagnostic frameworks for configuration management, register access, test orchestration, and automated debug procedures.
  • Develop diagnostics for SERDES, Ethernet, PCIe, and UCIe/chiplet interfaces, including training, BER, eye margining, and packet-processing validation.
  • Correlate RTL verification, emulation, firmware, and silicon behavior while debugging functional, timing, clocking, and protocol issues.

Requirements

  • Bachelor’s degree with 10+ years of relevant experience or Master’s degree with 5+ years of relevant experience.
  • Strong experience in ASIC bring-up, post-silicon validation, and hardware-software debugging.
  • Strong programming skills in Python, which is mandatory, together with C/C++ and scripting.
  • Experience building diagnostic frameworks, automation tools, test orchestration systems, and regression integrations.

Nice to have

  • Experience with SERDES, UCIe/chiplet architectures, or networking ASICs.
  • Familiarity with packet processor SDKs and emulation platforms.
  • Experience with BER testing tools and SERDES tuning or margining.
  • Exposure to CI and regression infrastructure for silicon validation.

Culture & Benefits

  • Work on next-generation AI infrastructure and high-performance silicon solutions.
  • Collaborate with an experienced engineering team spanning silicon, packaging, optics, software, and systems.
  • Contribute directly to technologies intended to improve AI data-center performance, power efficiency, capital costs, and reliability.
  • Base compensation is determined according to skills, experience, qualifications, work location, market trends, and comparable employee compensation.

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