Principal SerDes Bring-up Validation Engineer (AI)

Location: San Jose, California, United States

Salary: $185,000–$240,000 per year, depending on experience, level, and business need. The role may also be eligible for discretionary bonuses, incentives, and benefits.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and a software suite integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.

What you will do

• Lead end-to-end post-silicon bring-up, characterization, and validation strategies for high-speed PHYs and retimers.
• Translate product and design requirements into test objectives, pass/fail criteria, validation plans, and schedules.
• Execute block-level bring-up, functional and parametric testing, interoperability checks, and performance benchmarking.
• Build automated test, data capture, analysis, and regression frameworks for mixed-signal test benches.
• Debug failures across analog, digital, firmware, package, and protocol layers using lab measurements, waveform analysis, and system-level testing.
• Collaborate with design, firmware, system engineering, package, and manufacturing teams to deliver root-cause analyses, compliance reports, and improvement recommendations.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 8–12 years of hands-on experience in mixed-signal and high-speed laboratory environments.
• Experience with post-silicon validation and bring-up of high-speed PHYs or retimers.
• Deep knowledge of NRZ, PAM4, PLLs, CTLE, DFE, FFE, transmitter equalization, jitter, CDR/PLL behavior, crosstalk, and power integrity.
• Strong Python and C/C++ programming skills for test automation, data analysis, and firmware interaction.
• Experience with protocol analyzers, BERTs, real-time and sampling oscilloscopes, TDRs, VNAs, and related high-speed validation equipment.

Nice to have

• MS or PhD in Electrical Engineering or a related field.
• Experience designing and debugging signal-integrity characterization and demo boards.
• Knowledge of IEEE 802.3 Ethernet standards, Ethernet PHY validation, link training, auto-negotiation, and compliance testing.
• Experience with I2C, I3C, SPI, and UART interfaces.
• Ability to translate SI/PI simulation results into laboratory test plans and design or process improvements.

Culture & Benefits

• Work with mixed-signal, firmware, system engineering, and manufacturing teams on AI infrastructure connectivity products.
• Contribute to a diverse and inclusive environment that encourages varied ideas, backgrounds, and experiences.
• Potential eligibility for discretionary bonus, incentives, and benefits.