Digital - SerDes Digital Design Lead

Location: Bay Area, United States; on-site

Company

hirify.global is a chiplet startup developing high-performance, manufacturable interconnect and SerDes IP for data center and AI/ML systems.

What you will do

• Lead micro-architecture and RTL implementation for 224G PAM4 and 448G SerDes transmitter and receiver datapaths.
• Design DSP-based equalization, CDR loop logic, adaptation engines, PHY controllers, lane alignment, deskew, and rate-matching logic.
• Architect low-latency RS-FEC encoder and decoder blocks, including KP4/KP8 implementations and interleaving.
• Drive lint, CDC/RDC, synthesis optimization, timing closure, DFT collaboration, and physical-design integration through tapeout signoff.
• Collaborate with analog and mixed-signal teams on AFE integration, DAC/ADC interfaces, calibration, AMS co-simulation, and PHY bring-up.
• Support link training, auto-negotiation, firmware-accessible configuration, post-silicon characterization, and silicon debug.

Requirements

• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• 12+ years of digital design experience in high-speed SerDes, PHY, or transceiver IP, including tapeout experience at 112G PAM4 or higher.
• Expert RTL design skills with SystemVerilog and deep knowledge of synthesis, timing closure, CDC/RDC, and DFT.
• Expertise in SerDes DSP architectures, including FFE, DFE, MLSE, CTLE controls, CDR dynamics, and PAM4 adaptation and calibration.
• Working knowledge of IEEE 802.3, OIF CEI, RS-FEC KP4/KP8, and die-to-die standards such as UCIe.
• Hands-on experience with advanced process nodes, digital-analog integration, calibration state machines, and mixed-signal simulation environments.

Nice to have

• Experience with optical/electrical interconnects, VCSEL, EML, chiplet D2D interfaces, DRAM PHYs, or HBM memory interfaces.
• Participation in standards bodies or experience with emerging 224G/448G interconnect specifications.

Culture & Benefits

• Work with a cross-functional team focused on first-principles engineering and high-volume manufacturable products.
• Collaborate across digital, analog/mixed-signal, verification, DFT, physical design, and backend teams.
• Benefits are described as excellent; the role is full-time and on-site.