Staff Verification Engineer (SerDes)

Location: Bay Area, Vancouver, or Toronto; onsite Monday–Friday

Company

hirify.global is an early-stage chiplet startup developing high-performance technologies for chiplet-based systems.

What you will do

• Lead verification of SerDes, PHYs, DSP blocks, TX/RX equalization, and CDR.
• Define PHY verification architecture and develop SystemVerilog/UVM environments and test cases.
• Execute block- and chip-level verification plans and maintain regression environments.
• Integrate third-party VIPs and coordinate feature and bug tracking.
• Perform GLS simulations for functional verification and power calculations.
• Collaborate with design engineers, track progress toward RTL freeze, and mentor junior verification engineers.

Requirements

• BS degree and 7+ years of design verification experience, including 4+ years with PHYs or high-speed interfaces.
• Deep expertise in SerDes/PCIe PHY, TX/RX equalization, and CDR verification.
• Strong SystemVerilog and UVM expertise, including test environments and assertion coding.
• Experience verifying mixed-signal IPs and integrating VIPs.
• Ability to work onsite Monday–Friday in the Bay Area, Vancouver, or Toronto.

Nice to have

• 10+ years of experience with demonstrated verification technical leadership.
• Formal verification experience with JasperGold or VC Formal.
• GLS simulation experience and Python, Perl, or Tcl scripting.
• Experience with third-party regression management and coverage analysis tools.

Culture & Benefits

• Fast-paced early-stage startup environment.
• Cross-functional collaboration with engineering experts.
• Full-time employment with excellent benefits.