Staff Verification Engineer (SerDes)

Location: Bay Area, Vancouver, or Toronto. On-site Monday through Friday.

Company

hirify.global is an early-stage chiplet startup developing technologies for chiplet-based systems focused on power, area, manufacturability, and design flexibility.

What you will do

• Lead verification for SerDes, PHYs, DSP blocks, TX/RX equalization, and CDR.
• Define PHY verification architecture and develop SystemVerilog/UVM-based environments and test cases for block and chip level.
• Develop verification plans, maintain regression environments, and track test-plan progress toward RTL freeze.
• Collaborate with design teams to ensure design quality and integrate third-party VIPs while coordinating feature and bug tracking.
• Perform GLS simulations for functional verification and power calculations.
• Mentor junior verification engineers and contribute technical leadership in a cross-functional engineering team.

Requirements

• BS degree and 7 years of verification experience, including 4+ years in PHY or high-speed interfaces.
• Deep verification expertise in SerDes/PCIe PHY, TX/RX equalization, and CDR.
• Strong expertise in UVM and SystemVerilog, including test-environment and assertion coding.
• Experience verifying mixed-signal IPs and integrating VIPs.

Nice to have

• 10+ years of experience with demonstrated verification technical leadership.
• Formal verification experience with JasperGold or VC Formal.
• Experience with GLS simulations.
• Python, Perl, or Tcl scripting for design verification.
• Proficiency with third-party tools for regression management and coverage analysis.

Culture & Benefits

• Fast-paced early-stage startup environment.
• On-site work Monday through Friday.
• Cross-functional collaboration with engineering experts.
• Fun work environment and excellent benefits.