ASIC Chip Design Lead (AI Infrastructure)

Location: Saratoga, California, United States

Company

hirify.global is a Silicon Valley hardware startup developing silicon, packaging, software, and systems that accelerate AI data center performance.

What you will do

• Develop, review, and debug production-quality RTL in Verilog and SystemVerilog.
• Own RTL blocks from specification through signoff and translate architecture requirements into pipelines, control logic, datapaths, interfaces, and corner-case handling.
• Collaborate with Physical Design on synthesis, place-and-route timing, hierarchy, floorplanning, congestion, area, and power optimization.
• Partner with Design Verification to debug functional and performance issues, review coverage, and drive bugs through closure.
• Own full-chip RTL integration, chip-level synthesis, constraints, timing closure, and delivery of timing-clean netlists.
• Lead technical execution through design checklists, quality gates, methodology improvements, and hands-on technical authority.

Requirements

• Strong hands-on experience in RTL design and micro-architecture.
• Proven experience with full-chip integration and timing closure.
• Led at least one full-chip tape-out within the last three years with direct responsibility for design signoff and Physical Design handoff.
• Deep understanding of synthesis, static timing analysis, and Physical Design collaboration.
• Experience refactoring RTL to resolve timing, area, and congestion challenges.
• Ability to work cross-functionally with architecture, verification, firmware, and Physical Design teams in fast-moving environments.

Nice to have

• Silicon bring-up, post-silicon debugging, and RTL-to-silicon correlation experience.
• Experience defining and refining SDC constraints and improving post-layout timing.
• Knowledge of high-performance networking architectures and Ethernet-based systems.
• Familiarity with Ultra Ethernet, UCIe, or chiplet-based system design.

Culture & Benefits

• Work on AI infrastructure technology targeting higher performance, GPU utilization, reliability, and lower capital and power costs.
• Join an experienced engineering organization spanning silicon, packaging, optics, software, and systems.
• Contribute directly to products validated by leading hyperscalers.
• Base salary is determined according to skills, experience, qualifications, work location, market trends, and comparable employee compensation.